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Searched refs:res_pool (Results 1 – 25 of 102) sorted by relevance

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/linux/drivers/bus/fsl-mc/
A Dfsl-mc-allocator.c60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
79 res_pool->free_count++; in fsl_mc_resource_pool_add_device()
80 res_pool->max_count++; in fsl_mc_resource_pool_add_device()
128 res_pool->free_count > res_pool->max_count) { in fsl_mc_resource_pool_remove_device()
146 res_pool->free_count--; in fsl_mc_resource_pool_remove_device()
147 res_pool->max_count--; in fsl_mc_resource_pool_remove_device()
218 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_allocate()
223 res_pool->free_count--; in fsl_mc_resource_allocate()
243 res_pool->free_count >= res_pool->max_count) in fsl_mc_resource_free()
250 res_pool->free_count++; in fsl_mc_resource_free()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
100 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
112 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
127 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
135 if (res_pool->hubbub) { in dcn31_init_hw()
137 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
141 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn31_init_hw()
213 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn31_init_hw()
257 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn31_init_hw()
270 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn31_init_hw()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
135 struct resource_pool *res_pool = dc->res_pool; in dcn35_init_hw() local
152 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn35_init_hw()
162 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn35_init_hw()
166 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn35_init_hw()
207 if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init) in dcn35_init_hw()
208 res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub); in dcn35_init_hw()
288 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn35_init_hw()
303 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn35_init_hw()
1352 dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i); in dcn35_root_clock_control()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c228 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
231 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
232 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
243 if (res_pool->hubbub) { in dcn201_init_hw()
244 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
248 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
294 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn201_init_hw()
298 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
331 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()
382 struct mpc *mpc = dc->res_pool->mpc; in dcn201_plane_atomic_disconnect()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c425 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
474 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
552 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); in dcn30_disable_writeback()
626 struct resource_pool *res_pool = dc->res_pool; in dcn30_init_hw() local
637 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn30_init_hw()
666 if (res_pool->hubbub) { in dcn30_init_hw()
668 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn30_init_hw()
672 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn30_init_hw()
719 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn30_init_hw()
791 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn30_init_hw()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c778 struct resource_pool *res_pool = dc->res_pool; in dcn32_init_hw() local
789 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn32_init_hw()
811 if (res_pool->hubbub) { in dcn32_init_hw()
812 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn32_init_hw()
816 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn32_init_hw()
874 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn32_init_hw()
961 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn32_init_hw()
975 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn32_init_hw()
1650 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { in dcn32_init_blank()
1664 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { in dcn32_init_blank()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c838 dc->res_pool->dccg, in dcn20_enable_stream_timing()
1913 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); in dcn20_program_pipe()
2316 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); in dcn20_post_unlock_program_front_end()
2641 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); in dcn20_init_vm_ctx()
3015 dc->res_pool->dccg, in dcn20_enable_stream()
3077 struct resource_pool *res_pool = dc->res_pool; in dcn20_fpga_init_hw() local
3085 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn20_fpga_init_hw()
3125 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn20_fpga_init_hw()
3129 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
3164 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn20_fpga_init_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c219 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
240 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
241 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
263 if (res_pool->hubbub) { in dcn401_init_hw()
264 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
270 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn401_init_hw()
328 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn401_init_hw()
417 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn401_init_hw()
427 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn401_init_hw()
456 struct mpc *mpc = dc->res_pool->mpc; in dcn401_get_mcm_lut_xable_from_pipe_ctx()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c151 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
1462 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1531 dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s); in dcn10_init_pipes()
1549 struct resource_pool *res_pool = dc->res_pool; in dcn10_init_hw() local
1564 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) in dcn10_init_hw()
1565 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn10_init_hw()
1578 if (res_pool->dccg && res_pool->hubbub) { in dcn10_init_hw()
1580 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn10_init_hw()
1584 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn10_init_hw()
2047 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, in dcn10_cursor_lock()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
A Ddcn351_hwseq.c45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c211 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
213 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
214 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
263 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
264 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
364 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
381 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
383 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
417 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control( in dcn314_dpp_root_clock_control()
418 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on); in dcn314_dpp_root_clock_control()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
376 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
655 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_drr_admissable()
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/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
159 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
180 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
189 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
274 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
275 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
551 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
553 dc->res_pool->link_encoders[i] != NULL) { in link_enc_cfg_get_next_avail_link_enc()
554 link_enc = dc->res_pool->link_encoders[i]; in link_enc_cfg_get_next_avail_link_enc()
582 link->dc->res_pool->funcs->link_encs_assign) { in link_enc_cfg_get_link_enc()
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A Ddc.c358 if (!dc->res_pool) in destroy_link_encoders()
604 dmcu = dc->res_pool->dmcu; in dc_stream_forward_crc_window()
866 if (dc->res_pool && dc->res_pool->funcs->link_encs_assign) in dc_destruct()
1066 if (!dc->res_pool) in dc_construct()
1074 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
1332 dc->res_pool->stream_enc[j]); in disable_vbios_mode_if_required()
1338 dc->res_pool->dp_clock_source, in disable_vbios_mode_if_required()
1388 if (dc->res_pool->dmcu != NULL) in dc_create()
1676 dc->res_pool->stream_enc[i]); in dc_validate_boot_timing()
1745 dc->res_pool->dp_clock_source, in dc_validate_boot_timing()
[all …]
A Ddc_resource.c224 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
229 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
233 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
331 if (res_pool != NULL) { in dc_create_resource_pool()
349 return res_pool; in dc_create_resource_pool()
355 if (dc->res_pool) in dc_destroy_resource_pool()
356 dc->res_pool->funcs->destroy(&dc->res_pool); in dc_destroy_resource_pool()
3748 if (dc->res_pool == NULL) in dc_resource_is_dsc_encoding_supported()
4079 dc->res_pool, in dc_validate_global_state()
4085 dc->res_pool, in dc_validate_global_state()
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A Ddc_state.c304 if (dc->res_pool) in dc_state_construct()
388 if (state->stream_count >= dc->res_pool->timing_generator_count) { in dc_state_add_stream()
398 state, dc->res_pool, stream); in dc_state_add_stream()
423 dc->current_state, dc->res_pool, stream, 1); in dc_state_remove_stream()
425 state, dc->res_pool, stream); in dc_state_remove_stream()
463 new_ctx, cur_ctx, dc->res_pool, in remove_mpc_combine_for_stream()
473 struct resource_pool *pool = dc->res_pool; in dc_state_add_plane()
513 dc->current_state, dc->res_pool, stream, in dc_state_add_plane()
543 struct resource_pool *pool = dc->res_pool; in dc_state_remove_plane()
924 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_state_remove_phantom_streams_and_planes()
/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_hpo_dp.c118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_edid_parser.c35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1843 dsc = dc->res_pool->dscs[i]; in clean_up_dsc_blocks()
1853 se = dc->res_pool->stream_enc[i]; in clean_up_dsc_blocks()
1931 dc->res_pool->dccg, in dce110_enable_accelerated_mode()
2192 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2309 dc->res_pool, in dce110_reset_hw_ctx_wrap()
2360 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dce110_setup_audio_dto()
2382 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2781 xfm = dc->res_pool->transforms[i]; in init_hw()
2833 abm = dc->res_pool->abm; in init_hw()
2837 dmcu = dc->res_pool->dmcu; in init_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer_debug.c81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
85 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
113 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
191 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
233 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
290 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
330 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
385 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
416 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
491 struct resource_pool *pool = dc->res_pool; in dcn10_clear_otpc_underflow()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
A Ddcn35_pg_cntl.c85 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) in pg_cntl35_dsc_pg_control()
86 pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( in pg_cntl35_dsc_pg_control()
87 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
148 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { in pg_cntl35_dsc_pg_control()
150 pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( in pg_cntl35_dsc_pg_control()
151 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_edp_panel_control.c559 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
560 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
607 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
608 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
678 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
679 psr = dc->res_pool->psr; in edp_setup_psr()
782 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
857 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
872 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
955 replay = dc->res_pool->replay; in edp_setup_replay()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
A Ddcn21_hwseq.c83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
184 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
217 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
259 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
292 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
/linux/drivers/gpu/drm/amd/display/dc/link/
A Dlink_factory.c394 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
395 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
498 if (link->dc->res_pool->funcs->link_init) in construct_phy()
499 link->dc->res_pool->funcs->link_init(link); in construct_phy()
612 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
626 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
627 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
631 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
638 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
800 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()

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