Searched refs:reserved_bits (Results 1 – 9 of 9) sorted by relevance
347 u64 reserved_bits, diff; in intel_pmu_set_msr() local395 reserved_bits = pmu->reserved_bits; in intel_pmu_set_msr()398 reserved_bits ^= HSW_IN_TX_CHECKPOINTED; in intel_pmu_set_msr()399 if (data & reserved_bits) in intel_pmu_set_msr()535 pmu->reserved_bits ^= HSW_IN_TX; in intel_pmu_refresh()557 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; in intel_pmu_refresh()
1261 const u64 reserved_bits = GENMASK_ULL(63, 56) | in vmx_restore_vmx_basic() local1267 BUILD_BUG_ON(feature_bits & reserved_bits); in vmx_restore_vmx_basic()1275 if (!is_bitwise_subset(vmx_basic, data, feature_bits | reserved_bits)) in vmx_restore_vmx_basic()1361 const u64 reserved_bits = BIT_ULL(31) | GENMASK_ULL(13, 9); in vmx_restore_vmx_misc() local1366 BUILD_BUG_ON(feature_bits & reserved_bits); in vmx_restore_vmx_misc()1373 if (!is_bitwise_subset(vmx_misc, data, feature_bits | reserved_bits)) in vmx_restore_vmx_misc()
31 reserved_bits:6; member
165 data &= ~pmu->reserved_bits; in amd_pmu_set_msr()207 pmu->reserved_bits = 0xfffffff000280000ull; in amd_pmu_refresh()
202 u8 reserved_bits : 7; member
769 pmu->reserved_bits = 0xffffffff00200000ull; in kvm_pmu_refresh()
685 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | in kvm_set_apic_base() local688 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) in kvm_set_apic_base()3818 u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB); in kvm_set_msr_common() local3826 reserved_bits |= PRED_CMD_IBPB; in kvm_set_msr_common()3829 reserved_bits |= PRED_CMD_SBPB; in kvm_set_msr_common()3833 reserved_bits |= PRED_CMD_IBPB; in kvm_set_msr_common()3836 reserved_bits |= PRED_CMD_SBPB; in kvm_set_msr_common()3838 if (data & reserved_bits) in kvm_set_msr_common()
736 uint32_t reserved_bits : 28; /**< Reversed */ member750 uint32_t reserved_bits : 28; /**< Reversed bits */ member
557 u64 reserved_bits; member
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