| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | sdhci-msm.yaml | 20 - qcom,sdhci-msm-v4
24 - qcom,apq8084-sdhci
25 - qcom,ipq4019-sdhci
26 - qcom,ipq8074-sdhci
27 - qcom,msm8226-sdhci
28 - qcom,msm8953-sdhci
29 - qcom,msm8974-sdhci
52 - qcom,sdx55-sdhci
53 - qcom,sdx65-sdhci
176 - $ref: sdhci-common.yaml#
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| A D | brcm,sdhci-brcmstb.yaml | 18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
20 - const: brcm,sdhci-brcmstb
23 - brcm,bcm2712-sdhci
24 - brcm,bcm74165b0-sdhci
25 - brcm,bcm7445-sdhci
26 - brcm,bcm7425-sdhci
27 - const: brcm,sdhci-brcmstb
59 sdhci,auto-cmd12:
87 compatible = "brcm,bcm7216-sdhci",
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| A D | arasan,sdhci.yaml | 18 const: arasan,sdhci-5.1
50 - const: arasan,sdhci-5.1
56 - const: arasan,sdhci-8.9a
62 - const: arasan,sdhci-8.9a
72 - const: arasan,sdhci-5.1
78 - const: arasan,sdhci-5.1
84 - const: arasan,sdhci-5.1
209 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
254 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
272 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
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| A D | brcm,iproc-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
20 - brcm,bcm2835-sdhci
22 - brcm,sdhci-iproc-cygnus
23 - brcm,sdhci-iproc
24 - brcm,bcm7211a0-sdhci
35 Handle to core clock for the sdhci controller.
37 sdhci,auto-cmd12:
56 compatible = "brcm,sdhci-iproc-cygnus";
61 sdhci,auto-cmd12;
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| A D | aspeed,sdhci.yaml | 5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
42 "^sdhci@[0-9a-f]+$":
50 - aspeed,ast2400-sdhci
51 - aspeed,ast2500-sdhci
52 - aspeed,ast2600-sdhci
62 sdhci,auto-cmd12:
92 sdhci0: sdhci@100 {
93 compatible = "aspeed,ast2500-sdhci";
96 sdhci,auto-cmd12;
100 sdhci1: sdhci@200 {
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| A D | nvidia,tegra20-sdhci.yaml | 24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
26 - nvidia,tegra114-sdhci
27 - nvidia,tegra124-sdhci
28 - nvidia,tegra210-sdhci
29 - nvidia,tegra186-sdhci
30 - nvidia,tegra194-sdhci
66 - const: sdhci
213 - const: sdhci
276 reset-names = "sdhci";
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| A D | sdhci.txt | 7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
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| A D | marvell,xenon-sdhci.yaml | 26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
31 - marvell,armada-ap807-sdhci
32 - marvell,ac5-sdhci
33 - const: marvell,armada-ap806-sdhci
36 - const: marvell,armada-3700-sdhci
37 - const: marvell,sdhci-xenon
46 "marvell,armada-3700-sdhci" in below.
206 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
244 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
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| A D | atmel,sama5d2-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml#
20 - atmel,sama5d2-sdhci
21 - microchip,sam9x60-sdhci
24 - microchip,sam9x7-sdhci
25 - microchip,sama7g5-sdhci
26 - const: microchip,sam9x60-sdhci
64 - $ref: sdhci-common.yaml#
70 - atmel,sama5d2-sdhci
85 compatible = "atmel,sama5d2-sdhci";
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| A D | sdhci-omap.txt | 8 - compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
9 Should be "ti,omap3-sdhci" for omap3 controllers
10 Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
11 Should be "ti,omap5-sdhci" for omap5 controllers
12 Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
13 Should be "ti,k2g-sdhci" for K2G
14 Should be "ti,am335-sdhci" for am335x controllers
15 Should be "ti,am437-sdhci" for am437x controllers
36 compatible = "ti,dra7-sdhci";
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| A D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
64 mmc0: sdhci@fe81e000 {
65 compatible = "st,sdhci";
77 mmc1: sdhci@9080000 {
78 compatible = "st,sdhci-stih407", "st,sdhci";
93 mmc0: sdhci@9060000 {
94 compatible = "st,sdhci-stih407", "st,sdhci";
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| A D | sdhci-spear.txt | 4 and the properties used by the sdhci-spear driver.
7 - compatible: "st,spear300-sdhci"
14 sdhci@fc000000 {
15 compatible = "st,spear300-sdhci";
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| A D | fujitsu,sdhci-fujitsu.yaml | 4 $id: http://devicetree.org/schemas/mmc/fujitsu,sdhci-fujitsu.yaml#
19 - const: socionext,synquacer-sdhci
20 - const: fujitsu,mb86s70-sdhci-3.0
22 - fujitsu,mb86s70-sdhci-3.0
60 compatible = "fujitsu,mb86s70-sdhci-3.0";
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| A D | sdhci-am654.yaml | 14 - $ref: sdhci-common.yaml#
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
22 - ti,am64-sdhci-8bit
23 - ti,am654-sdhci-5.1
24 - ti,j721e-sdhci-4bit
25 - ti,j721e-sdhci-8bit
27 - const: ti,j7200-sdhci-8bit
28 - const: ti,j721e-sdhci-8bit
30 - const: ti,j7200-sdhci-4bit
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| A D | npcm,sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/npcm,sdhci.yaml#
18 - nuvoton,npcm750-sdhci
19 - nuvoton,npcm845-sdhci
41 compatible = "nuvoton,npcm750-sdhci";
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| A D | samsung,s3c6410-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/samsung,s3c6410-sdhci.yaml#
16 - samsung,s3c6410-sdhci
17 - samsung,exynos4210-sdhci
52 - samsung,exynos4210-sdhci
71 compatible = "samsung,exynos4210-sdhci";
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| A D | sdhci-pxa.yaml | 4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
18 const: marvell,armada-380-sdhci
40 - marvell,armada-380-sdhci
48 - const: sdhci
109 compatible = "marvell,armada-380-sdhci";
110 reg-names = "sdhci", "mbus", "conf-sdio3";
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| A D | marvell,dove-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml#
7 title: Marvell sdhci-dove controller
18 const: marvell,dove-sdhci
40 compatible = "marvell,dove-sdhci";
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| A D | brcm,kona-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/brcm,kona-sdhci.yaml#
13 - $ref: sdhci-common.yaml#
17 const: brcm,kona-sdhci
43 compatible = "brcm,kona-sdhci";
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| A D | microchip,sdhci-pic32.txt | 4 and the properties used by the sdhci-pic32 driver.
7 - compatible: Should be "microchip,pic32mzda-sdhci"
19 sdhci@1f8ec000 {
20 compatible = "microchip,pic32mzda-sdhci";
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| A D | sdhci-milbeaut.txt | 7 - compatible: "socionext,milbeaut-m10v-sdhci-3.0"
12 "iface" - clock used for sdhci interface
13 "core" - core clock for sdhci controller
21 compatible = "socionext,milbeaut-m10v-sdhci-3.0";
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| A D | microchip,dw-sparx5-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
56 compatible = "microchip,dw-sparx5-sdhci";
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| /linux/drivers/mmc/host/ |
| A D | Makefile | 13 obj-$(CONFIG_MMC_SDHCI) += sdhci.o
14 obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
15 sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
16 sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
17 obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
18 obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
19 obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
20 obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
23 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
96 obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
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| A D | sdhci-spear.c | 46 struct spear_sdhci *sdhci; in sdhci_probe() local
74 sdhci = sdhci_priv(host); in sdhci_probe()
78 if (IS_ERR(sdhci->clk)) { in sdhci_probe()
79 ret = PTR_ERR(sdhci->clk); in sdhci_probe()
84 ret = clk_prepare_enable(sdhci->clk); in sdhci_probe()
90 ret = clk_set_rate(sdhci->clk, 50000000); in sdhci_probe()
93 clk_get_rate(sdhci->clk)); in sdhci_probe()
112 clk_disable_unprepare(sdhci->clk); in sdhci_probe()
132 clk_disable_unprepare(sdhci->clk); in sdhci_remove()
148 clk_disable(sdhci->clk); in sdhci_suspend()
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| A D | sdhci-of-aspeed.c | 112 struct aspeed_sdhci *sdhci, in aspeed_sdc_configure_8bit_mode() argument
121 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
123 info &= ~sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
217 struct aspeed_sdhci *sdhci; in aspeed_sdhci_configure_phase() local
221 sdhci = sdhci_pltfm_priv(sdhci_priv(host)); in aspeed_sdhci_configure_phase()
223 if (!sdhci->phase_desc) in aspeed_sdhci_configure_phase()
226 params = &sdhci->phase_map.phase[host->timing]; in aspeed_sdhci_configure_phase()
228 aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); in aspeed_sdhci_configure_phase()
240 struct aspeed_sdhci *sdhci; in aspeed_sdhci_set_clock() local
245 sdhci = sdhci_pltfm_priv(pltfm_host); in aspeed_sdhci_set_clock()
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