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Searched refs:shared_dpll (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.c141 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
144 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
489 new_crtc_state->shared_dpll = NULL; in intel_put_dpll()
491 if (!old_crtc_state->shared_dpll) in intel_put_dpll()
511 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; in intel_shared_dpll_swap_state() local
637 crtc_state->shared_dpll = pll; in ibx_get_dpll()
1233 crtc_state->shared_dpll = pll; in hsw_get_dpll()
1954 crtc_state->shared_dpll = pll; in skl_get_dpll()
2439 crtc_state->shared_dpll = pll; in bxt_get_dpll()
4687 if (new_crtc_state->shared_dpll) in intel_shared_dpll_state_verify()
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A Dintel_pch_display.c252 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
383 if (crtc_state->shared_dpll == in ilk_pch_enable()
526 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); in ilk_pch_get_config()
527 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
A Dintel_modeset_setup.c92 if (crtc_state->shared_dpll) in intel_crtc_disable_noatomic_begin()
94 crtc_state->shared_dpll, in intel_crtc_disable_noatomic_begin()
95 &crtc_state->shared_dpll->state); in intel_crtc_disable_noatomic_begin()
576 crtc_state->shared_dpll && in has_bogus_dpll_config()
A Dintel_ddi.c268 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1534 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1578 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1622 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1688 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1732 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1775 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1883 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1951 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
4087 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_port_pll_type()
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A Dintel_display.c1343 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; in intel_encoders_update_prepare()
1700 if (pipe_crtc_state->shared_dpll) in hsw_crtc_enable()
2055 if (crtc_state->shared_dpll) in get_crtc_power_domains()
3063 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
3442 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
3842 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
4566 saved_state->shared_dpll = secondary_crtc_state->shared_dpll; in copy_joiner_crtc_state_modeset()
4629 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
5400 PIPE_CONF_CHECK_P(shared_dpll); in intel_pipe_config_compare()
A Dintel_display_types.h706 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; member
1180 struct intel_shared_dpll *shared_dpll; member
A Dintel_lvds.c248 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); in intel_pre_enable_lvds()
A Dintel_fdi.c918 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); in hsw_fdi_link_train()
A Dintel_dpll.c1773 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1775 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
A Dicl_dsi.c655 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()

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