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Searched refs:stream_res (Results 1 – 25 of 61) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_dio.c89 pipe_ctx->stream_res.stream_enc->id, in reset_dio_stream_encoder()
107 pipe_ctx->stream_res.tg->inst, in setup_dio_stream_attribute()
122 pipe_ctx->stream_res.audio != NULL); in setup_dio_stream_attribute()
207 pipe_ctx->stream_res.stream_enc, in setup_dio_audio_output()
212 pipe_ctx->stream_res.stream_enc, in setup_dio_audio_output()
222 pipe_ctx->stream_res.stream_enc); in enable_dio_audio_packet()
225 pipe_ctx->stream_res.stream_enc, false); in enable_dio_audio_packet()
236 pipe_ctx->stream_res.stream_enc, true); in disable_dio_audio_packet()
238 if (pipe_ctx->stream_res.audio) { in disable_dio_audio_packet()
241 pipe_ctx->stream_res.stream_enc); in disable_dio_audio_packet()
[all …]
A Dlink_hwss_hpo_dp.c37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder()
181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output()
182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output()
189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet()
190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet()
195 if (pipe_ctx->stream_res.audio) in disable_hpo_dp_audio_packet()
196 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( in disable_hpo_dp_audio_packet()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c114 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
121 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
127 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
128 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
170 pipe_ctx->stream_res.tg, in dcn314_update_odm()
179 odm_pipe->stream_res.opp, in dcn314_update_odm()
183 if (pipe_ctx->stream_res.dsc) { in dcn314_update_odm()
375 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); in dcn314_resync_fifo_dccg_dio()
402 pipe->stream_res.tg, in dcn314_resync_fifo_dccg_dio()
406 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn314_resync_fifo_dccg_dio()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1088 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) in dce110_enable_audio_stream()
1098 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); in dce110_enable_audio_stream()
1124 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) in dce110_disable_audio_stream()
1498 pipe_ctx->stream_res.tg, in program_scaler()
1522 pipe_ctx->stream_res.tg, in dce110_enable_stream_timing()
1529 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); in dce110_enable_stream_timing()
1616 pipe_ctx->stream_res.opp, in dce110_apply_single_controller_ctx_to_hw()
2297 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); in dce110_reset_hw_ctx_wrap()
2302 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); in dce110_reset_hw_ctx_wrap()
2576 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in program_surface_visibility()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c394 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
404 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
408 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
521 pipe_ctx->stream_res.tg, in dcn31_reset_back_end_for_pipe()
523 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); in dcn31_reset_back_end_for_pipe()
524 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn31_reset_back_end_for_pipe()
533 pipe_ctx->stream_res.tg, NULL); in dcn31_reset_back_end_for_pipe()
544 else if (pipe_ctx->stream_res.audio) in dcn31_reset_back_end_for_pipe()
548 if (pipe_ctx->stream_res.audio) { in dcn31_reset_back_end_for_pipe()
550 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); in dcn31_reset_back_end_for_pipe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c377 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
384 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
391 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
433 pipe_ctx->stream_res.tg, in dcn35_update_odm()
442 odm_pipe->stream_res.opp, in dcn35_update_odm()
894 pipe_ctx->stream_res.opp, in dcn35_enable_plane()
946 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); in dcn35_plane_atomic_disable()
1124 cur_pipe->stream_res.opp != new_pipe->stream_res.opp && in dcn35_calc_blocks_to_ungate()
1129 cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc && in dcn35_calc_blocks_to_ungate()
1134 cur_pipe->stream_res.tg != new_pipe->stream_res.tg && in dcn35_calc_blocks_to_ungate()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c723 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); in dcn20_plane_atomic_disable()
1205 struct stream_resource *stream_res = &pipe_ctx->stream_res; in dcn20_blank_pixel_data() local
1455 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn20_pipe_control_lock()
1457 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn20_pipe_control_lock()
1460 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn20_pipe_control_lock()
1462 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); in dcn20_pipe_control_lock()
1565 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) in dcn20_detect_pipe_changes()
1567 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) in dcn20_detect_pipe_changes()
1576 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) in dcn20_detect_pipe_changes()
1985 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, in dcn20_program_pipe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c449 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
465 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
488 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
497 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
832 pipe_ctx->stream_res.tg); in dp_set_test_pattern()
835 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); in dp_set_test_pattern()
858 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); in dp_set_test_pattern()
859 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
861 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
863 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1041 !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) { in dcn10_enable_stream_timing()
1042 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
1112 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); in dcn10_reset_back_end_for_pipe()
1330 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); in dcn10_plane_atomic_disable()
1947 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn10_pipe_control_lock()
1949 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); in dcn10_pipe_control_lock()
1984 if (!pipe_ctx->stream_res.stream_enc || !pipe_ctx->stream_res.tg) in delay_cursor_until_vupdate()
2934 struct stream_resource *stream_res = &pipe_ctx->stream_res; in dcn10_blank_pixel_data() local
2952 stream_res->tg, in dcn10_blank_pixel_data()
2957 stream_res->tg->funcs->set_blank(stream_res->tg, blank); in dcn10_blank_pixel_data()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c407 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
1076 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in dcn32_update_dsc_on_stream()
1083 pipe_ctx->stream_res.tg, in dcn32_update_dsc_on_stream()
1090 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); in dcn32_update_dsc_on_stream()
1134 pipe_ctx->stream_res.tg, in dcn32_update_odm()
1253 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); in dcn32_resync_fifo_dccg_dio()
1280 pipe->stream_res.tg, in dcn32_resync_fifo_dccg_dio()
1284 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn32_resync_fifo_dccg_dio()
1793 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg) in dcn32_is_pipe_topology_transition_seamless()
1802 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp) in dcn32_is_pipe_topology_transition_seamless()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c842 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, in link_set_dsc_on_stream()
853 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in link_set_dsc_on_stream()
860 pipe_ctx->stream_res.tg, in link_set_dsc_on_stream()
883 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); in link_set_dsc_on_stream()
905 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in link_set_dsc_on_stream()
1343 pipe_ctx->stream_res.stream_enc, in deallocate_mst_payload()
1752 pipe_ctx->stream_res.stream_enc, in link_reduce_mst_payload()
1824 pipe_ctx->stream_res.stream_enc, in link_increase_mst_payload()
2414 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); in link_set_dpms_off()
2480 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); in link_set_dpms_on()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c842 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
850 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
865 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
886 pipe_ctx->stream_res.opp, in dcn401_enable_stream_timing()
892 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { in dcn401_enable_stream_timing()
921 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); in dcn401_enable_stream_timing()
1574 if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) in update_dsc_for_odm_change()
1598 otg_master->stream_res.tg, in dcn401_update_odm()
1603 otg_master->stream_res.tg, in dcn401_update_odm()
1713 tg = pipe->stream_res.tg; in dcn401_interdependent_update_lock()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c325 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
820 pipe_ctx->stream_res.stream_enc, in dcn30_set_avmute()
824 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { in dcn30_set_avmute()
825 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
826 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
827 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
828 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
829 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
852 pipe_ctx->stream_res.stream_enc, in dcn30_update_info_frame()
857 pipe_ctx->stream_res.stream_enc, in dcn30_update_info_frame()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c310 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
319 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
324 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
345 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
385 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
521 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
542 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
544 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
547 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
549 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c2095 if (otg_master->stream_res.tg) in resource_get_odm_slice_dst_width()
2214 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp) in resource_is_odm_topology_changed()
2257 pipe->stream_res.opp->inst, in resource_log_pipe()
3452 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg, in acquire_resource_from_hw_enabled_state()
3729 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; in resource_map_pool_resources()
3737 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; in resource_map_pool_resources()
4613 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) in pipe_need_reprogram()
4620 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) in pipe_need_reprogram()
4633 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) in pipe_need_reprogram()
4636 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) in pipe_need_reprogram()
[all …]
A Ddc.c680 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
721 tg = pipe->stream_res.tg; in dc_stream_get_crc()
1551 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); in program_timing_sync()
1598 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); in program_timing_sync()
3312 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, in commit_planes_do_stream_update()
3316 odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, in commit_planes_do_stream_update()
3373 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); in commit_planes_do_stream_update()
3396 if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) in commit_planes_do_stream_update()
5894 if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause) in dc_notify_vsync_int_state()
5895 …pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->… in dc_notify_vsync_int_state()
[all …]
A Ddc_hw_sequencer.c710 …block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp-… in hwss_build_fast_sequence()
717 …equence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
874 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) in hwss_program_manual_trigger()
875 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); in hwss_program_manual_trigger()
1006 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); in hwss_wait_for_all_blank_complete()
1021 tg = otg_master->stream_res.tg; in hwss_wait_for_odm_update_pending_complete()
1074 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) in hwss_wait_for_outstanding_hw_updates()
1075 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); in hwss_wait_for_outstanding_hw_updates()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
A Ddcn21_hwseq.c181 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
214 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
215 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe()
249 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
250 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level()
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc()
192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility()
200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color()
251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler()
260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler()
261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1393 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1399 if (!pipe_ctx->stream_res.dsc) { in dcn20_add_dsc_to_stream_resource()
1421 if (pipe_ctx->stream_res.dsc) in remove_dsc_from_stream_resource()
1496 next_odm_pipe->stream_res.dsc = NULL; in dcn20_split_stream_for_odm()
1551 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; in dcn20_split_stream_for_odm()
1701 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) in dcn20_validate_dsc()
1809 if (odm_pipe->stream_res.dsc) in dcn20_merge_pipes_for_validate()
1813 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); in dcn20_merge_pipes_for_validate()
1838 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); in dcn20_merge_pipes_for_validate()
2189 sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg; in dcn20_acquire_free_pipe_for_layer()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c143 old_pipe->stream_res.tg == new_pipe->stream_res.tg && in dcn35_disable_otg_wa()
148 new_pipe->stream_res.stream_enc && in dcn35_disable_otg_wa()
149 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && in dcn35_disable_otg_wa()
150 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); in dcn35_disable_otg_wa()
155 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn35_disable_otg_wa()
156 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa()
160 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa()
179 if (pipe_ctx->stream_res.tg && in dcn35_update_clocks_update_dtb_dto()
180 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
181 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c895 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
919 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
922 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1137 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1141 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1152 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1160 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1170 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1171 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1183 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c118 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn316_disable_otg_wa()
119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()

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