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Searched refs:tf_shift (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
196 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap()
198 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap()
281 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
283 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
337 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
364 reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
538 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp1_program_input_csc()
[all …]
A Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
564 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument
574 dpp->tf_shift = tf_shift; in dpp1_construct()
A Ddcn10_dpp_dscl.c51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
365 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp_cm.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
175 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
178 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
182 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
187 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
191 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
195 reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
341 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
343 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
421 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap()
[all …]
A Ddcn30_dpp.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
134 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
136 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
673 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
677 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
682 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
684 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
686 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
690 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1512 const struct dcn3_dpp_shift *tf_shift, in dpp3_construct() argument
[all …]
A Ddcn30_dpp.h564 const struct dcn3_dpp_shift *tf_shift; member
583 const struct dcn3_dpp_shift *tf_shift,
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
A Ddcn20_dpp_cm.c47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
250 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap()
252 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap()
339 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
341 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
417 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
426 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
430 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
A Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
411 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument
421 dpp->tf_shift = tf_shift; in dpp2_construct()
A Ddcn20_dpp.h682 const struct dcn2_dpp_shift *tf_shift; member
779 const struct dcn2_dpp_shift *tf_shift,
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
A Ddcn35_dpp.c37 ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \
123 const struct dcn35_dpp_shift *tf_shift, in dpp35_construct() argument
127 (const struct dcn3_dpp_shift *)(tf_shift), in dpp35_construct()
A Ddcn35_dpp.h59 const struct dcn35_dpp_shift *tf_shift,
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.h61 const struct dcn201_dpp_shift *tf_shift; member
80 const struct dcn201_dpp_shift *tf_shift,
A Ddcn201_dpp.c42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
302 const struct dcn201_dpp_shift *tf_shift, in dpp201_construct() argument
312 dpp->tf_shift = tf_shift; in dpp201_construct()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
220 cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A; in dpp401_program_cursor_csc()
222 cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A; in dpp401_program_cursor_csc()
A Ddcn401_dpp.c43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
266 const struct dcn401_dpp_shift *tf_shift, in dpp401_construct() argument
276 dpp->tf_shift = tf_shift; in dpp401_construct()
A Ddcn401_dpp.h658 const struct dcn401_dpp_shift *tf_shift; member
677 const struct dcn401_dpp_shift *tf_shift,
A Ddcn401_dpp_dscl.c51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
379 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp401_dscl_set_scl_filter()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
A Ddcn32_dpp.c151 const struct dcn3_dpp_shift *tf_shift, in dpp32_construct() argument
161 dpp->tf_shift = tf_shift; in dpp32_construct()
A Ddcn32_dpp.h36 const struct dcn3_dpp_shift *tf_shift,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c475 static const struct dcn201_dpp_shift tf_shift = { variable
639 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
A Ddcn10_resource.c359 static const struct dcn_dpp_shift tf_shift = { variable
592 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
A Ddcn302_resource.c530 static const struct dcn3_dpp_shift tf_shift = { variable
545 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
A Ddcn303_resource.c509 static const struct dcn3_dpp_shift tf_shift = { variable
524 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c442 static const struct dcn2_dpp_shift tf_shift = { variable
510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c415 static const struct dcn3_dpp_shift tf_shift = { variable
724 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()

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