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Searched refs:tile (Results 1 – 25 of 169) sorted by relevance

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/linux/drivers/gpu/drm/xe/
A Dxe_tile.c89 tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt), in xe_tile_alloc()
91 if (!tile->mem.ggtt) in xe_tile_alloc()
93 tile->mem.ggtt->tile = tile; in xe_tile_alloc()
95 tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL); in xe_tile_alloc()
96 if (!tile->mem.vram_mgr) in xe_tile_alloc()
117 tile->xe = xe; in xe_tile_init_early()
118 tile->id = id; in xe_tile_init_early()
124 tile->primary_gt = xe_gt_alloc(tile); in xe_tile_init_early()
128 xe_pcode_init(tile); in xe_tile_init_early()
139 err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr); in tile_ttm_mgr_init()
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A Dxe_pcode.c85 return pcode_mailbox_status(tile); in __pcode_mailbox_rw()
104 mutex_lock(&tile->pcode.lock); in xe_pcode_write_timeout()
106 mutex_unlock(&tile->pcode.lock); in xe_pcode_write_timeout()
115 mutex_lock(&tile->pcode.lock); in xe_pcode_read()
117 mutex_unlock(&tile->pcode.lock); in xe_pcode_read()
177 mutex_lock(&tile->pcode.lock); in xe_pcode_request()
194 drm_err(&tile_to_xe(tile)->drm, in xe_pcode_request()
202 mutex_unlock(&tile->pcode.lock); in xe_pcode_request()
242 mutex_lock(&tile->pcode.lock); in xe_pcode_init_min_freq_table()
284 mutex_lock(&tile->pcode.lock); in xe_pcode_ready()
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A Dxe_irq.c273 return tile->media_gt; in pick_engine_gt()
412 struct xe_tile *tile; in dg1_irq_handler() local
509 if ((tile->media_gt && in gt_irq_reset()
527 gt_irq_reset(tile); in xelp_irq_reset()
537 if (tile->id == 0) in dg1_irq_reset()
540 gt_irq_reset(tile); in dg1_irq_reset()
557 struct xe_tile *tile; in vf_irq_reset() local
571 gt_irq_reset(tile); in vf_irq_reset()
577 struct xe_tile *tile; in xe_irq_reset() local
607 struct xe_tile *tile; in vf_irq_postinstall() local
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A Dxe_vram.c232 for_each_if(t->id < tile->id) in tile_vram_size()
272 struct xe_tile *tile; in vram_fini() local
280 for_each_tile(tile, xe, id) in vram_fini()
281 tile->mem.vram.mapping = NULL; in vram_fini()
294 struct xe_tile *tile; in xe_vram_probe() local
323 for_each_tile(tile, xe, id) { in xe_vram_probe()
332 if (!tile->mem.vram.io_size) { in xe_vram_probe()
341 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) in xe_vram_probe()
344 …tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_si… in xe_vram_probe()
346 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size, in xe_vram_probe()
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A Dxe_tile_sysfs.c27 struct xe_tile *tile = arg; in tile_sysfs_fini() local
29 kobject_put(tile->sysfs); in tile_sysfs_fini()
32 int xe_tile_sysfs_init(struct xe_tile *tile) in xe_tile_sysfs_init() argument
34 struct xe_device *xe = tile_to_xe(tile); in xe_tile_sysfs_init()
44 kt->tile = tile; in xe_tile_sysfs_init()
46 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); in xe_tile_sysfs_init()
52 tile->sysfs = &kt->base; in xe_tile_sysfs_init()
54 err = xe_vram_freq_sysfs_init(tile); in xe_tile_sysfs_init()
58 return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile); in xe_tile_sysfs_init()
A Dxe_mmio.c29 struct xe_tile *tile; in tiles_fini() local
33 tile->mmio.regs = NULL; in tiles_fini()
51 struct xe_tile *tile; in mmio_multi_tile_setup() local
92 for_each_tile(tile, xe, id) { in mmio_multi_tile_setup()
94 tile->mmio.regs = regs; in mmio_multi_tile_setup()
120 struct xe_tile *tile; in mmio_extension_setup() local
130 tile->mmio_ext.regs = regs; in mmio_extension_setup()
204 val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); in xe_mmio_read8()
219 val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); in xe_mmio_read16()
235 writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); in xe_mmio_write32()
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A Dxe_ggtt.c110 struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt : in ggtt_update_access_counter()
111 ggtt->tile->media_gt; in ggtt_update_access_counter()
129 xe_tile_assert(ggtt->tile, addr < ggtt->size); in xe_ggtt_set_pte()
146 xe_tile_assert(ggtt->tile, start < end); in xe_ggtt_clear()
214 struct xe_device *xe = tile_to_xe(ggtt->tile); in xe_ggtt_init_early()
229 ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M; in xe_ggtt_init_early()
239 ggtt->pt_ops = (ggtt->tile->media_gt && in xe_ggtt_init_early()
335 xe = tile_to_xe(ggtt->tile); in xe_ggtt_node_remove()
442 xe_tile_assert(ggtt->tile, start < end); in xe_ggtt_node_insert_balloon()
455 if (xe_gt_WARN(ggtt->tile->primary_gt, err, in xe_ggtt_node_insert_balloon()
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A Dxe_pt.c61 u8 id = tile->id; in __xe_pt_empty_pte()
260 struct xe_tile *tile; member
618 .tile = tile, in xe_pt_stage_bind()
753 struct xe_tile *tile; member
818 .tile = tile, in xe_pt_zap_ptes()
1389 struct xe_tile *tile; member
1518 .tile = tile, in xe_pt_stage_unbind()
1752 struct xe_tile *tile, in op_prepare() argument
1918 struct xe_tile *tile, in op_commit() argument
1999 .tile_id = tile->id, in xe_pt_update_ops_run()
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A Dxe_pcode.h13 void xe_pcode_init(struct xe_tile *tile);
16 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
18 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
19 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
21 #define xe_pcode_write(tile, mbox, val) \ argument
22 xe_pcode_write_timeout(tile, mbox, val, 1)
24 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
A Dxe_pt.h30 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,
33 void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,
38 int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops);
39 struct dma_fence *xe_pt_update_ops_run(struct xe_tile *tile,
41 void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops);
42 void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops);
44 bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dnv20.c35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
51 tile->zcomp |= tile->tag->offset; in nv20_fb_tile_comp()
54 tile->zcomp |= 0x08000000; in nv20_fb_tile_comp()
62 tile->addr = 0; in nv20_fb_tile_fini()
63 tile->limit = 0; in nv20_fb_tile_fini()
64 tile->pitch = 0; in nv20_fb_tile_fini()
65 tile->zcomp = 0; in nv20_fb_tile_fini()
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A Dnv30.c35 tile->addr = (0 << 4); in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
57 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv30_fb_tile_comp()
58 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; in nv30_fb_tile_comp()
60 tile->zcomp |= 0x10000000; in nv30_fb_tile_comp()
121 .tile.regions = 8,
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A Dnv10.c33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
59 .tile.regions = 8,
60 .tile.init = nv10_fb_tile_init,
61 .tile.fini = nv10_fb_tile_fini,
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A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
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A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
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A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
61 .tile.init = nv44_fb_tile_init,
62 .tile.fini = nv20_fb_tile_fini,
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A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
241 fb->func->tile.fini(fb, i, &fb->tile.region[i]); in nvkm_fb_dtor()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dnv44.c44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
61 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
63 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
66 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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/linux/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_mman.c52 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
93 const struct tile *tile, in check_partial_mapping() argument
111 tile->tiling, tile->stride, err); in check_partial_mapping()
186 const struct tile *tile, in check_partial_mappings() argument
199 tile->tiling, tile->stride, err); in check_partial_mappings()
352 struct tile tile; in igt_partial_tiling() local
370 struct tile tile; in igt_partial_tiling() local
398 tile.stride = tile.width * pitch; in igt_partial_tiling()
426 tile.stride = tile.width * pitch; in igt_partial_tiling()
489 struct tile tile; in igt_smoke_tiling() local
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/linux/drivers/gpu/ipu-v3/
A Dipu-image-convert.c877 tile = &image->tile[i]; in calc_tile_dimensions()
883 tile->stride = tile->width; in calc_tile_dimensions()
884 tile->rot_stride = tile->height; in calc_tile_dimensions()
897 tile->width, tile->height, tile->left, tile->top); in calc_tile_dimensions()
1008 top = image->tile[tile].top; in calc_tile_offsets_planar()
1026 image->tile[tile].offset = y_off; in calc_tile_offsets_planar()
1027 image->tile[tile].u_off = u_off; in calc_tile_offsets_planar()
1069 image->tile[tile].u_off = 0; in calc_tile_offsets_packed()
1070 image->tile[tile++].v_off = 0; in calc_tile_offsets_packed()
1421 s_image->tile[tile].width, in convert_start()
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/linux/drivers/gpu/drm/xe/tests/
A Dxe_bo.c95 offset = xe_device_ccs_bytes(tile_to_xe(tile), bo->size); in ccs_test_migrate()
120 unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile); in ccs_test_run_tile()
123 kunit_info(test, "Testing vram id %u\n", tile->id); in ccs_test_run_tile()
159 struct xe_tile *tile; in ccs_test_run_device() local
175 for_each_tile(tile, xe, id) { in ccs_test_run_device()
179 ccs_test_run_tile(xe, tile, test); in ccs_test_run_device()
197 unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile); in evict_test_run_tile()
203 dev_name(xe->drm.dev), tile->id); in evict_test_run_tile()
336 struct xe_tile *tile; in evict_test_run_device() local
346 for_each_tile(tile, xe, id) in evict_test_run_device()
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