| /linux/drivers/gpu/drm/i915/gvt/ |
| A D | fb_decoder.c | 154 u32 tiled, int stride_mask, int bpp) in intel_vgpu_get_stride() argument
162 switch (tiled) { in intel_vgpu_get_stride()
182 tiled); in intel_vgpu_get_stride()
226 plane->tiled = val & PLANE_CTL_TILED_MASK; in intel_vgpu_decode_primary_plane()
241 plane->tiled = val & DISP_TILED; in intel_vgpu_decode_primary_plane()
265 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, in intel_vgpu_decode_primary_plane()
435 plane->tiled = !!(val & SPRITE_TILED); in intel_vgpu_decode_sprite_plane()
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| A D | fb_decoder.h | 108 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ member
123 u8 tiled; /* X-tiled */ member
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| A D | dmabuf.c | 276 switch (p.tiled) { in vgpu_get_plane_info()
293 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); in vgpu_get_plane_info()
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | fsl-vdoa.txt | 5 is to reorder video data from the macroblock tiled order produced by the CODA
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| /linux/include/uapi/drm/ |
| A D | omap_drm.h | 61 } tiled; /* (for tiled formats) */ member
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| /linux/drivers/gpu/drm/sun4i/ |
| A D | sun4i_frontend.c | 270 bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED); in sun4i_frontend_drm_format_to_input_mode() local
278 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR in sun4i_frontend_drm_format_to_input_mode()
283 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR in sun4i_frontend_drm_format_to_input_mode()
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| /linux/drivers/gpu/drm/omapdrm/ |
| A D | omap_gem.c | 1338 tiler_align(gem2fmt(flags), &gsize.tiled.width, in omap_gem_new()
1339 &gsize.tiled.height); in omap_gem_new()
1341 size = tiler_size(gem2fmt(flags), gsize.tiled.width, in omap_gem_new()
1342 gsize.tiled.height); in omap_gem_new()
1344 omap_obj->width = gsize.tiled.width; in omap_gem_new()
1345 omap_obj->height = gsize.tiled.height; in omap_gem_new()
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| /linux/drivers/gpu/drm/exynos/ |
| A D | exynos_drm_gsc.c | 449 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) in gsc_src_set_fmt() argument
515 if (tiled) in gsc_src_set_fmt()
636 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) in gsc_dst_set_fmt() argument
702 if (tiled) in gsc_dst_set_fmt()
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| A D | exynos_drm_fimc.c | 364 static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) in fimc_src_set_fmt() argument
406 if (tiled) in fimc_src_set_fmt()
630 static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) in fimc_dst_set_fmt() argument
679 if (tiled) in fimc_dst_set_fmt()
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| /linux/drivers/gpu/drm/ci/xfails/ |
| A D | i915-whl-fails.txt | 10 kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
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| A D | i915-amly-fails.txt | 9 kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
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| A D | i915-cml-fails.txt | 12 kms_ccs@crc-primary-rotation-180-yf-tiled-ccs,Timeout
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| /linux/drivers/gpu/drm/radeon/ |
| A D | radeon_gem.c | 805 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled) in radeon_align_pitch() argument
808 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; in radeon_align_pitch()
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| A D | r600_cs.c | 2380 u32 header, cmd, count, tiled; in r600_dma_cs_parse() local
2396 tiled = GET_DMA_T(header); in r600_dma_cs_parse()
2405 if (tiled) { in r600_dma_cs_parse()
2436 if (tiled) { in r600_dma_cs_parse()
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| A D | radeon.h | 532 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
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| /linux/Documentation/userspace-api/media/v4l/ |
| A D | pixfmt-yuv-planar.rst | 20 tiled. Padding may be supported at the end of the lines, and the line stride of
153 - 16x32 / 16x16 tiles tiled low bits
431 lower two bits is said to be tiled since each bytes contains the lower two
709 P010 and tiled P010
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| /linux/net/netfilter/ipvs/ |
| A D | Kconfig | 294 stored in a hash table. This table is tiled by each destination
297 tiled an amount proportional to the weights specified. The table
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| /linux/Documentation/userspace-api/media/drivers/ |
| A D | cx2341x-uapi.rst | 10 format of a YUV frame is 16x16 linear tiled NV12 (V4L2_PIX_FMT_NV12_16L16).
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| /linux/Documentation/admin-guide/media/ |
| A D | ivtv.rst | 162 is a 16x16 linear tiled NV12 format (V4L2_PIX_FMT_NV12_16L16)
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| /linux/Documentation/gpu/ |
| A D | tegra.rst | 146 with Tegra-specific flags. This is useful for buffers that should be tiled, or
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| /linux/Documentation/userspace-api/ |
| A D | dma-buf-alloc-exchange.rst | 128 making use of tiled access and possibly also compression. For example, the
319 implementation-specific: some will internally use tiled layouts which are not
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_gem.c | 919 bool tiled) in amdgpu_gem_align_pitch() argument
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| A D | com.fuc | 515 // Setup to handle a tiled surface
|