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/linux/Documentation/userspace-api/media/v4l/
A Dmetafmt-pisp-be.rst17 The PiSP Back End processes images in tiles, and its configuration requires
30 to be processed and is therefore shared across all the tiles of the image. So
32 across all tiles from the same frame.
40 As the ISP processes images in tiles, each set of tiles parameters describe how
42 parameters consist of 160 bytes of data and to process a batch of tiles several
43 sets of tiles parameters are required.
A Dpixfmt-yuv-planar.rst102 - 64x32 tiles
111 - 16x16 tiles
125 - 4x4 tiles
146 - 4x4 tiles
153 - 16x32 / 16x16 tiles tiled low bits
324 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
329 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
369 pixels in 2D 8x128 tiles, and stores tiles linearly in memory.
398 10 bits pixels in 2D 8x128 tiles, and stores tiles linearly in memory.
418 composed of 16x32 luma tiles, and 16x16 chroma tiles. Each tiles is 640 bytes
[all …]
/linux/drivers/gpu/drm/xe/
A Dxe_device.h58 return &xe->tiles[0]; in xe_device_get_root_tile()
89 gt = xe->tiles[gt_id].primary_gt; in xe_device_get_gt()
125 for_each_if((tile__) = &(xe__)->tiles[(id__)])
129 for_each_if((tile__) = &(xe__)->tiles[(id__)])
A Dxe_gsc_proxy.c344 struct xe_gt *gt = xe->tiles[0].media_gt; in xe_gsc_proxy_component_bind()
359 struct xe_gt *gt = xe->tiles[0].media_gt; in xe_gsc_proxy_component_unbind()
A Dxe_device_types.h394 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; member
A Dxe_query.c561 struct xe_guc *guc = &xe->tiles[0].primary_gt->uc.guc; in query_uc_fw_version()
581 media_gt = xe->tiles[0].primary_gt; in query_uc_fw_version()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
A Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
A Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
A Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
A Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
/linux/Documentation/devicetree/bindings/arm/
A Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
A Darm,vexpress-juno.yaml18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
130 description: When describing tiles consisting of more than one DCC, its
139 the connection between the motherboard and any tiles. Sometimes the
/linux/Documentation/admin-guide/perf/
A Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
A Dvdec_vp9_req_lat_if.c275 struct vdec_vp9_slice_tiles tiles; member
887 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile() local
897 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile()
898 tiles->actual_rows = 0; in vdec_vp9_slice_setup_tile()
911 tiles->mi_rows[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
912 if (tiles->mi_rows[i]) in vdec_vp9_slice_setup_tile()
913 tiles->actual_rows++; in vdec_vp9_slice_setup_tile()
1079 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile_buffer() local
1105 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile_buffer()
1131 tiles->size[i][j] = size; in vdec_vp9_slice_setup_tile_buffer()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_fb.c890 unsigned int tiles; in intel_adjust_tile_offset() local
896 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
898 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
899 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
1001 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
1016 tiles = *x / tile_width; in intel_compute_aligned_offset()
1019 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
1518 unsigned int tiles; in calc_plane_normal_size() local
1523 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * in calc_plane_normal_size()
1530 tiles++; in calc_plane_normal_size()
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/linux/arch/arm/include/debug/
A Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
/linux/drivers/video/fbdev/core/
A DKconfig205 where the screen is divided into rectangular sections (tiles), whereas
208 parameters in terms of number of tiles instead of number of pixels.
212 terms of number of tiles in the x- and y-axis.
/linux/drivers/pinctrl/qcom/
A Dpinctrl-msm.h160 const char *const *tiles; member
/linux/Documentation/devicetree/bindings/media/
A Draspberrypi,pispbe.yaml16 in tiles and produces images consumable by applications.
/linux/Documentation/ABI/testing/
A Dsysfs-driver-hid-picolcd41 tiles get changed and it's not appropriate to expect the application
/linux/arch/arm/boot/dts/arm/
A Darm-realview-eb.dts42 * core tiles.
/linux/drivers/media/platform/raspberrypi/pisp_be/
A Dpisp_be.c196 dma_addr_t tiles; member
290 pispbe_wr(pispbe, PISP_BE_TILE_ADDR_LO_REG, lower_32_bits(job->tiles)); in pispbe_queue_job()
291 pispbe_wr(pispbe, PISP_BE_TILE_ADDR_HI_REG, upper_32_bits(job->tiles)); in pispbe_queue_job()
484 job->tiles = pispbe->config_dma_addr + in pispbe_prepare_job()
486 offsetof(struct pisp_be_tiles_config, tiles); in pispbe_prepare_job()
/linux/Documentation/devicetree/bindings/clock/
A Darm,syscon-icst.yaml30 In the core modules and logic tiles, the ICST is a configurable clock fed

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