| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| A D | dc_common.c | 65 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible()
74 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_mall_phantom.c | 122 pipe->top_pipe = NULL; in merge_pipes_for_subvp()
128 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in merge_pipes_for_subvp()
129 struct pipe_ctx *top_pipe = pipe->top_pipe; in merge_pipes_for_subvp() local
132 top_pipe->bottom_pipe = bottom_pipe; in merge_pipes_for_subvp()
134 bottom_pipe->top_pipe = top_pipe; in merge_pipes_for_subvp()
136 pipe->top_pipe = NULL; in merge_pipes_for_subvp()
194 if (pipe->stream && !pipe->top_pipe) { in get_num_free_pipes()
255 if (pipe->plane_state && !pipe->top_pipe && in assign_subvp_pipe()
319 if (pipe->stream && !pipe->top_pipe && in enough_pipes_for_subvp()
616 if (pipe->plane_state && !pipe->top_pipe && in dml2_svp_validate_static_schedulability()
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| A D | dml2_dc_resource_mgmt.c | 115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
158 && (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) { in find_pipes_assigned_to_plane()
563 struct pipe_ctx *top_pipe) in add_plane_to_blend_tree() argument
568 if (top_pipe) in add_plane_to_blend_tree()
573 state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].top_pipe = top_pipe; in add_plane_to_blend_tree()
576 top_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]]; in add_plane_to_blend_tree()
581 return top_pipe; in add_plane_to_blend_tree()
725 if (pipe->top_pipe) in remove_pipes_from_blend_trees()
726 pipe->top_pipe->bottom_pipe = pipe->bottom_pipe; in remove_pipes_from_blend_trees()
729 pipe->bottom_pipe = pipe->top_pipe; in remove_pipes_from_blend_trees()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1387 if (pipe_ctx->top_pipe) in dcn20_add_dsc_to_stream_resource()
1501 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { in dcn20_split_stream_for_odm()
1503 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; in dcn20_split_stream_for_odm()
1548 if (!next_odm_pipe->top_pipe) in dcn20_split_stream_for_odm()
1805 odm_pipe->top_pipe = NULL; in dcn20_merge_pipes_for_validate()
1833 hsplit_pipe->top_pipe = NULL; in dcn20_merge_pipes_for_validate()
1881 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) in dcn20_validate_apply_pipe_split_flags()
1971 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn20_validate_apply_pipe_split_flags()
1975 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) in dcn20_validate_apply_pipe_split_flags()
2013 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn20_validate_apply_pipe_split_flags()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 129 pipe->top_pipe = NULL; in dcn32_merge_pipes_for_subvp()
135 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn32_merge_pipes_for_subvp()
136 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn32_merge_pipes_for_subvp() local
139 top_pipe->bottom_pipe = bottom_pipe; in dcn32_merge_pipes_for_subvp()
141 bottom_pipe->top_pipe = top_pipe; in dcn32_merge_pipes_for_subvp()
143 pipe->top_pipe = NULL; in dcn32_merge_pipes_for_subvp()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1588 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { in resource_build_scaling_params()
1881 !pipe_ctx->top_pipe && in resource_is_pipe_type()
1997 while (opp_head->top_pipe) in resource_get_opp_head()
2038 other_pipe = pipe->top_pipe; in resource_get_mpc_slice_count()
2472 if (split_pipe->top_pipe && in acquire_first_split_pipe()
2476 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; in acquire_first_split_pipe()
2837 if (pipe_ctx->top_pipe) in resource_remove_dpp_pipes_for_plane_composition()
2845 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; in resource_remove_dpp_pipes_for_plane_composition()
2851 if (!pipe_ctx->top_pipe) in resource_remove_dpp_pipes_for_plane_composition()
3113 last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe; in release_dpp_pipe_and_remove_mpc_slice()
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| A D | dc_hw_sequencer.c | 322 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color() local
324 while (top_pipe->top_pipe) in get_mpctree_visual_confirm_color()
325 top_pipe = top_pipe->top_pipe; in get_mpctree_visual_confirm_color()
327 *color = pipe_colors[top_pipe->pipe_idx]; in get_mpctree_visual_confirm_color()
390 while (top_pipe_ctx->top_pipe != NULL) in get_hdr_visual_confirm_color()
391 top_pipe_ctx = top_pipe_ctx->top_pipe; in get_hdr_visual_confirm_color()
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| A D | dc_state.c | 153 if (cur_pipe->top_pipe) in dc_state_copy_internal()
154 cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_state_copy_internal()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1547 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1549 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1558 if (!sec_pipe->top_pipe) in dcn30_split_stream_for_mpc_or_odm()
1572 sec_pipe->bottom_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1575 sec_pipe->top_pipe = pri_pipe; in dcn30_split_stream_for_mpc_or_odm()
1740 pipe->top_pipe = NULL; in dcn30_internal_validate_bw()
1747 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn30_internal_validate_bw()
1748 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn30_internal_validate_bw() local
1751 top_pipe->bottom_pipe = bottom_pipe; in dcn30_internal_validate_bw()
1753 bottom_pipe->top_pipe = top_pipe; in dcn30_internal_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 1896 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn32_split_stream_for_mpc_or_odm()
1898 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn32_split_stream_for_mpc_or_odm()
1906 ASSERT(sec_pipe->top_pipe == NULL); in dcn32_split_stream_for_mpc_or_odm()
1908 if (!sec_pipe->top_pipe) in dcn32_split_stream_for_mpc_or_odm()
1925 sec_pipe->top_pipe = pri_pipe; in dcn32_split_stream_for_mpc_or_odm()
1991 if (pipe->top_pipe) { in dcn32_apply_merge_split_flags_helper()
1999 pipe->top_pipe = NULL; in dcn32_apply_merge_split_flags_helper()
2007 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn32_apply_merge_split_flags_helper()
2008 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn32_apply_merge_split_flags_helper() local
2013 bottom_pipe->top_pipe = top_pipe; in dcn32_apply_merge_split_flags_helper()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
945 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in calculate_vready_offset_for_group()
1332 pipe_ctx->top_pipe = NULL; in dcn10_plane_atomic_disable()
1745 if (pipe_ctx_old->top_pipe) in dcn10_reset_hw_ctx_wrap()
1940 if (!pipe || pipe->top_pipe) in dcn10_pipe_control_lock()
2028 if (!pipe || pipe->top_pipe) in dcn10_cursor_lock()
2548 if (!pipe_ctx->top_pipe in dcn10_enable_plane()
2584 if (pipe_ctx->top_pipe) { in dcn10_is_rear_mpo_fix_required()
2587 while (top->top_pipe) in dcn10_is_rear_mpo_fix_required()
3053 if (pipe_ctx->top_pipe || in dcn10_wait_for_pending_cleared()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 725 pipe_ctx->top_pipe = NULL; in dcn20_plane_atomic_disable()
847 if (pipe_ctx->top_pipe != NULL) in dcn20_enable_stream_timing()
1029 if (pipe_ctx->top_pipe == NULL in dcn20_set_output_transfer_func()
1359 if (!pipe_ctx->top_pipe in dcn20_enable_plane()
1381 if (!pipe || pipe->top_pipe) in dcn20_pipe_control_lock()
1849 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in calculate_vready_offset_for_group()
2083 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn20_program_front_end_for_ctx()
2158 !pipe->top_pipe && in dcn20_program_front_end_for_ctx()
2466 if (pipe_ctx->top_pipe == NULL) { in dcn20_update_bandwidth()
2666 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| A D | link_resource.c | 42 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) { in link_get_cur_link_res()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 117 if (pipe_ctx->top_pipe == NULL) { in dcn401_program_gamut_remap()
1055 for (test_pipe = pipe_ctx->top_pipe; test_pipe; in dcn401_can_pipe_disable_cursor()
1056 test_pipe = test_pipe->top_pipe) { in dcn401_can_pipe_disable_cursor()
1072 for (split_pipe = pipe_ctx->top_pipe; split_pipe; in dcn401_can_pipe_disable_cursor()
1073 split_pipe = split_pipe->top_pipe) in dcn401_can_pipe_disable_cursor()
1129 if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { in dcn401_set_cursor_position()
1212 pipe_ctx->top_pipe && in dcn401_set_cursor_position()
1213 (pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) { in dcn401_set_cursor_position()
1373 const struct pipe_ctx *top_pipe) in dcn401_wait_for_dcc_meta_propagation() argument
1376 const struct pipe_ctx *pipe_ctx = top_pipe; in dcn401_wait_for_dcc_meta_propagation()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
545 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in split_stream_across_pipes()
548 secondary_pipe->top_pipe = primary_pipe; in split_stream_across_pipes()
899 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1206 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1271 hsplit_pipe->bottom_pipe->top_pipe = pipe; in dcn_validate_bandwidth()
1274 hsplit_pipe->top_pipe = NULL; in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 60 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
534 if (pipe->top_pipe) in dcn201_pipe_control_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1426 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
1428 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; in dcn20_populate_dml_pipes_from_context()
1431 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
1433 first_pipe = first_pipe->top_pipe; in dcn20_populate_dml_pipes_from_context()
1442 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; in dcn20_populate_dml_pipes_from_context()
1594 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) in dcn20_populate_dml_pipes_from_context()
1663 split_pipe = res_ctx->pipe_ctx[i].top_pipe; in dcn20_populate_dml_pipes_from_context()
1666 split_pipe = split_pipe->top_pipe; in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| A D | dcn314_hwseq.c | 371 if (pipe->top_pipe || pipe->prev_odm_pipe) in dcn314_resync_fifo_dccg_dio()
445 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { in apply_symclk_on_tx_off_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 516 ASSERT(!pipe_ctx->top_pipe); in dcn31_reset_back_end_for_pipe()
583 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) in dcn31_reset_hw_ctx_wrap()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 417 …if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)… in dc_dmub_srv_populate_fams_pipe_info()
1006 for (test_pipe = pipe_ctx->top_pipe; test_pipe; in dc_can_pipe_disable_cursor()
1007 test_pipe = test_pipe->top_pipe) { in dc_can_pipe_disable_cursor()
1021 for (split_pipe = pipe_ctx->top_pipe; split_pipe; in dc_can_pipe_disable_cursor()
1022 split_pipe = split_pipe->top_pipe) in dc_can_pipe_disable_cursor()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| A D | dce_clk_mgr.c | 177 if (pipe_ctx->top_pipe) in dce_get_max_pixel_clock_for_all_paths()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_utils.c | 258 (dc_pipe->top_pipe == NULL || in dml21_populate_mall_allocation_size()
259 dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) && in dml21_populate_mall_allocation_size()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 2267 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) in dce110_reset_hw_ctx_wrap()
2351 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2389 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2443 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) in dce110_apply_ctx_to_hw()
2483 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) in dce110_apply_ctx_to_hw()
3115 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) in dce110_set_cursor_position()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 449 struct pipe_ctx *top_pipe; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 855 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
869 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) in dcn21_fast_validate_bw()
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