| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 334 ttu_regs->qos_level_low_wm); in print__ttu_regs_st()
337 ttu_regs->qos_level_high_wm); in print__ttu_regs_st()
340 ttu_regs->min_ttu_vblank); in print__ttu_regs_st()
343 ttu_regs->qos_level_flip); in print__ttu_regs_st()
370 ttu_regs->qos_level_fixed_l); in print__ttu_regs_st()
373 ttu_regs->qos_ramp_disable_l); in print__ttu_regs_st()
376 ttu_regs->qos_level_fixed_c); in print__ttu_regs_st()
379 ttu_regs->qos_ramp_disable_c); in print__ttu_regs_st()
382 ttu_regs->qos_level_fixed_cur0); in print__ttu_regs_st()
385 ttu_regs->qos_ramp_disable_cur0); in print__ttu_regs_st()
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| A D | display_mode_lib.h | 54 display_ttu_regs_st *ttu_regs,
72 display_ttu_regs_st *ttu_regs,
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| A D | dml1_display_rq_dlg_calc.h | 57 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_helpers.h | 44 …tu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_rq_dlg_calc_32.c | 208 display_ttu_regs_st *ttu_regs, in dml32_rq_dlg_get_dlg_reg() argument
267 memset(ttu_regs, 0, sizeof(*ttu_regs)); in dml32_rq_dlg_get_dlg_reg()
541 ttu_regs->qos_level_low_wm = 0; in dml32_rq_dlg_get_dlg_reg()
545 ttu_regs->qos_level_flip = 14; in dml32_rq_dlg_get_dlg_reg()
546 ttu_regs->qos_level_fixed_l = 8; in dml32_rq_dlg_get_dlg_reg()
547 ttu_regs->qos_level_fixed_c = 8; in dml32_rq_dlg_get_dlg_reg()
548 ttu_regs->qos_level_fixed_cur0 = 8; in dml32_rq_dlg_get_dlg_reg()
549 ttu_regs->qos_ramp_disable_l = 0; in dml32_rq_dlg_get_dlg_reg()
550 ttu_regs->qos_ramp_disable_c = 0; in dml32_rq_dlg_get_dlg_reg()
551 ttu_regs->qos_ramp_disable_cur0 = 0; in dml32_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_32.h | 65 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 305 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr; in dcn10_get_ttu_states() local
312 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_get_ttu_states()
313 …ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delive… in dcn10_get_ttu_states()
314 …ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per… in dcn10_get_ttu_states()
315 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1, in dcn10_get_ttu_states()
316 …ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disabl… in dcn10_get_ttu_states()
317 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_get_ttu_states()
318 … ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1); in dcn10_get_ttu_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_utils.c | 226 memset(&out->ttu_regs, 0, sizeof(out->ttu_regs)); in dml21_update_pipe_ctx_dchub_regs()
227 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; in dml21_update_pipe_ctx_dchub_regs()
228 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm; in dml21_update_pipe_ctx_dchub_regs()
229 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; in dml21_update_pipe_ctx_dchub_regs()
230 out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip; in dml21_update_pipe_ctx_dchub_regs()
239 out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l; in dml21_update_pipe_ctx_dchub_regs()
240 out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c; in dml21_update_pipe_ctx_dchub_regs()
241 out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0; in dml21_update_pipe_ctx_dchub_regs()
243 out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l; in dml21_update_pipe_ctx_dchub_regs()
244 out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c; in dml21_update_pipe_ctx_dchub_regs()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_util.c | 300 void dml_print_ttu_regs_st(const dml_display_ttu_regs_st *ttu_regs) in dml_print_ttu_regs_st() argument
304 dml_print("DML: qos_level_low_wm = 0x%x\n", ttu_regs->qos_level_low_wm); in dml_print_ttu_regs_st()
305 dml_print("DML: qos_level_high_wm = 0x%x\n", ttu_regs->qos_level_high_wm); in dml_print_ttu_regs_st()
306 dml_print("DML: min_ttu_vblank = 0x%x\n", ttu_regs->min_ttu_vblank); in dml_print_ttu_regs_st()
307 dml_print("DML: qos_level_flip = 0x%x\n", ttu_regs->qos_level_flip); in dml_print_ttu_regs_st()
316 dml_print("DML: qos_level_fixed_l = 0x%x\n", ttu_regs->qos_level_fixed_l); in dml_print_ttu_regs_st()
317 dml_print("DML: qos_ramp_disable_l = 0x%x\n", ttu_regs->qos_ramp_disable_l); in dml_print_ttu_regs_st()
318 dml_print("DML: qos_level_fixed_c = 0x%x\n", ttu_regs->qos_level_fixed_c); in dml_print_ttu_regs_st()
319 dml_print("DML: qos_ramp_disable_c = 0x%x\n", ttu_regs->qos_ramp_disable_c); in dml_print_ttu_regs_st()
320 dml_print("DML: qos_level_fixed_cur0 = 0x%x\n", ttu_regs->qos_level_fixed_cur0); in dml_print_ttu_regs_st()
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| A D | dml2_translation_helper.c | 1482 memset(&out->ttu_regs, 0, sizeof(out->ttu_regs)); in dml2_update_pipe_ctx_dchub_regs()
1483 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; in dml2_update_pipe_ctx_dchub_regs()
1484 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm; in dml2_update_pipe_ctx_dchub_regs()
1485 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; in dml2_update_pipe_ctx_dchub_regs()
1486 out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip; in dml2_update_pipe_ctx_dchub_regs()
1495 out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l; in dml2_update_pipe_ctx_dchub_regs()
1496 out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c; in dml2_update_pipe_ctx_dchub_regs()
1497 out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0; in dml2_update_pipe_ctx_dchub_regs()
1498 out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1; in dml2_update_pipe_ctx_dchub_regs()
1499 out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l; in dml2_update_pipe_ctx_dchub_regs()
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| A D | dml_display_rq_dlg_calc.h | 56 dml_display_ttu_regs_st *ttu_regs,
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| A D | display_mode_util.h | 57 __DML_DLL_EXPORT__ void dml_print_ttu_regs_st(const dml_display_ttu_regs_st *ttu_regs);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20v2.h | 63 display_ttu_regs_st *ttu_regs,
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| A D | display_rq_dlg_calc_20.h | 63 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.h | 63 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.h | 59 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.h | 59 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.h | 60 display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | hubp.h | 143 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
150 struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
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| A D | mem_input.h | 108 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 272 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr; in dcn10_log_hubp_states() local
276 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_log_hubp_states()
277 …ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delive… in dcn10_log_hubp_states()
278 …ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per… in dcn10_log_hubp_states()
279 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1, in dcn10_log_hubp_states()
280 …ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disabl… in dcn10_log_hubp_states()
281 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0, in dcn10_log_hubp_states()
282 … ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1); in dcn10_log_hubp_states()
2843 &pipe_ctx->ttu_regs, in dcn10_update_dchubp_dpp()
2849 &pipe_ctx->ttu_regs); in dcn10_update_dchubp_dpp()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_dchub_registers.h | 147 struct dml2_display_ttu_regs ttu_regs; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 460 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs; in dcn_bw_calc_rq_dlg_ttu() local
471 memset(ttu_regs, 0, sizeof(*ttu_regs)); in dcn_bw_calc_rq_dlg_ttu()
512 ttu_regs, in dcn_bw_calc_rq_dlg_ttu()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 455 struct _vcs_dpi_display_ttu_regs_st ttu_regs; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 1595 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; in dcn20_detect_pipe_changes()
1597 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; in dcn20_detect_pipe_changes()
1640 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || in dcn20_detect_pipe_changes()
1683 &pipe_ctx->ttu_regs, in dcn20_update_dchubp_dpp()
1695 &pipe_ctx->ttu_regs); in dcn20_update_dchubp_dpp()
2490 &pipe_ctx->ttu_regs, in dcn20_update_bandwidth()
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