| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | smu8_hwmgr.c | 104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
696 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
1031 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_populate_umdpstate_clocks()
1187 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1396 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback()
1572 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
1690 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks()
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| A D | processpptables.c | 1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1420 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1452 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1453 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1456 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1754 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1755 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
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| A D | smu7_hwmgr.c | 785 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
1521 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk = in smu7_populate_umdpstate_clocks() local
1522 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_populate_umdpstate_clocks()
1525 if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) { in smu7_populate_umdpstate_clocks()
1526 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk; in smu7_populate_umdpstate_clocks()
1531 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk; in smu7_populate_umdpstate_clocks()
1534 vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk; in smu7_populate_umdpstate_clocks()
2789 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); in smu7_patch_dependency_tables_with_leakage()
3195 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
3206 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
[all …]
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| A D | ppatomctrl.c | 1163 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1164 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1170 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1179 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | iceland_smumgr.c | 540 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
554 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
555 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
574 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
575 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
734 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
741 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
745 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in iceland_populate_ulv_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
1826 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in iceland_populate_smc_initial_state()
[all …]
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| A D | ci_smumgr.c | 419 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
773 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
782 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
783 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
798 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
799 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
967 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
974 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
978 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level()
1860 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in ci_populate_smc_initial_state()
[all …]
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| /linux/drivers/gpu/drm/radeon/ |
| A D | kv_dpm.c | 398 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
420 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
561 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
922 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1532 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1904 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
1945 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2149 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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| A D | r600_dpm.c | 924 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
936 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
947 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
959 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
1300 kfree(dyn_state->vddc_dependency_on_sclk.entries); in r600_free_extended_power_table()
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| A D | ci_dpm.c | 259 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
2293 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2299 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2316 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2550 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
3097 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3184 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3401 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3744 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
4877 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
[all …]
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| A D | btc_dpm.c | 2179 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2188 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2197 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
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| A D | si_dpm.c | 2985 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3091 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4093 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4096 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4098 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4111 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4113 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
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| A D | radeon_atombios.c | 3314 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in radeon_atom_get_voltage_evv()
3318 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in radeon_atom_get_voltage_evv()
3330 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in radeon_atom_get_voltage_evv()
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| A D | ni_dpm.c | 873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
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| A D | radeon.h | 1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; member
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| A D | kv_dpm.c | 77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
793 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
1154 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1770 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
2166 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2207 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2411 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
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| A D | legacy_dpm.c | 273 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
636 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
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| A D | si_dpm.c | 3502 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3608 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4614 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4617 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4619 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4632 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4634 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
6373 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
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| /linux/drivers/gpu/drm/amd/pm/inc/ |
| A D | amdgpu_dpm.h | 201 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | hwmgr.h | 631 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; member
|