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Searched refs:vgpu (Results 1 – 25 of 50) sorted by relevance

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/linux/drivers/gpu/drm/i915/gvt/
A Dvgpu.c47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
62 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); in populate_pvinfo_page()
69 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); in populate_pvinfo_page()
71 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); in populate_pvinfo_page()
273 vgpu = vzalloc(sizeof(*vgpu)); in intel_gvt_create_idle_vgpu()
274 if (!vgpu) in intel_gvt_create_idle_vgpu()
278 vgpu->gvt = gvt; in intel_gvt_create_idle_vgpu()
289 return vgpu; in intel_gvt_create_idle_vgpu()
292 vfree(vgpu); in intel_gvt_create_idle_vgpu()
309 vfree(vgpu); in intel_gvt_destroy_idle_vgpu()
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A Ddisplay.c89 if (edp_pipe_is_enabled(vgpu) && in pipe_is_enabled()
90 get_edp_pipe(vgpu) == pipe) in pipe_is_enabled()
290 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
320 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
351 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
388 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change()
533 struct intel_vgpu *vgpu; in vblank_timer_fn() local
602 intel_vgpu_port(vgpu, vgpu->display.port_num); in vgpu_update_vblank_emulation()
662 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
665 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
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A Dcfg_space.c97 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { in vgpu_pci_cfg_mem_write()
101 vgpu->d3_entered = true; in vgpu_pci_cfg_mem_write()
103 vgpu->id, pwr); in vgpu_pci_cfg_mem_write()
157 trap_gttmmio(vgpu, false); in emulate_pci_command_write()
158 map_aperture(vgpu, false); in emulate_pci_command_write()
160 trap_gttmmio(vgpu, true); in emulate_pci_command_write()
161 map_aperture(vgpu, true); in emulate_pci_command_write()
209 trap_gttmmio(vgpu, false); in emulate_pci_bar_write()
216 map_aperture(vgpu, false); in emulate_pci_bar_write()
390 trap_gttmmio(vgpu, false); in intel_vgpu_reset_cfg_space()
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A Dgvt.h112 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) argument
125 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) argument
424 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) argument
425 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) argument
428 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
430 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) argument
433 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
437 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
439 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) argument
441 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
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A Daperture_gm.c90 ret = alloc_gm(vgpu, true); in alloc_vgpu_gm()
95 vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu)); in alloc_vgpu_gm()
98 vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu)); in alloc_vgpu_gm()
180 _clear_vgpu_fence(vgpu); in free_vgpu_fence()
212 _clear_vgpu_fence(vgpu); in alloc_vgpu_fence()
309 free_vgpu_gm(vgpu); in intel_vgpu_free_resource()
310 free_vgpu_fence(vgpu); in intel_vgpu_free_resource()
311 free_resource(vgpu); in intel_vgpu_free_resource()
327 _clear_vgpu_fence(vgpu); in intel_vgpu_reset_resource()
362 free_vgpu_gm(vgpu); in intel_vgpu_alloc_resource()
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A Dmmio.c73 if (!vgpu || !p_data) in failsafe_emulate_mmio_rw()
76 gvt = vgpu->gvt; in failsafe_emulate_mmio_rw()
77 mutex_lock(&vgpu->vgpu_lock); in failsafe_emulate_mmio_rw()
95 mutex_unlock(&vgpu->vgpu_lock); in failsafe_emulate_mmio_rw()
116 if (vgpu->failsafe) { in intel_vgpu_emulate_mmio_read()
120 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_read()
191 if (vgpu->failsafe) { in intel_vgpu_emulate_mmio_write()
196 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_mmio_write()
318 if (!vgpu->mmio.vreg) in intel_vgpu_init_mmio()
333 vfree(vgpu->mmio.vreg); in intel_vgpu_clean_mmio()
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A Dedid.c148 intel_vgpu_init_i2c_edid(vgpu); in gmbus0_mmio_write()
188 reset_gmbus_controller(vgpu); in gmbus1_mmio_write()
222 vgpu->id, target_addr); in gmbus1_mmio_write()
242 intel_vgpu_init_i2c_edid(vgpu); in gmbus1_mmio_write()
274 vgpu_vreg(vgpu, offset) = wvalue; in gmbus1_mmio_write()
309 byte_data = edid_get_byte(vgpu); in gmbus3_mmio_read()
328 intel_vgpu_init_i2c_edid(vgpu); in gmbus3_mmio_read()
490 vgpu_vreg(vgpu, offset) = value; in intel_gvt_i2c_handle_aux_ch_write()
497 msg = vgpu_vreg(vgpu, offset + 4); in intel_gvt_i2c_handle_aux_ch_write()
508 vgpu_vreg(vgpu, offset) = in intel_gvt_i2c_handle_aux_ch_write()
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A Dkvmgt.c256 new->vgpu = vgpu; in __gvt_cache_add()
554 vgpu->region[vgpu->num_regions].type = type; in intel_vgpu_register_reg()
555 vgpu->region[vgpu->num_regions].subtype = subtype; in intel_vgpu_register_reg()
556 vgpu->region[vgpu->num_regions].ops = ops; in intel_vgpu_register_reg()
557 vgpu->region[vgpu->num_regions].size = size; in intel_vgpu_register_reg()
558 vgpu->region[vgpu->num_regions].flags = flags; in intel_vgpu_register_reg()
559 vgpu->region[vgpu->num_regions].data = data; in intel_vgpu_register_reg()
769 off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); in intel_vgpu_in_aperture()
840 return vgpu->region[index].ops->rw(vgpu, buf, count, in intel_vgpu_rw()
1043 vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) in intel_vgpu_mmap()
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A Dsched_policy.c55 struct intel_vgpu *vgpu; member
80 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice()
192 vgpu = vgpu_data->vgpu; in find_busy_vgpu()
200 vgpu = vgpu_data->vgpu; in find_busy_vgpu()
205 return vgpu; in find_busy_vgpu()
223 if (vgpu) { in tbs_sched_func()
320 data->vgpu = vgpu; in tbs_sched_init_vgpu()
411 ret = vgpu->gvt->scheduler.sched_ops->init_vgpu(vgpu); in intel_vgpu_init_sched_policy()
420 vgpu->gvt->scheduler.sched_ops->clean_vgpu(vgpu); in intel_vgpu_clean_sched_policy()
431 vgpu->gvt->scheduler.sched_ops->start_schedule(vgpu); in intel_vgpu_start_schedule()
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A Dhandlers.c195 vgpu->failsafe = true; in enter_failsafe_mode()
495 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()
533 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); in bdw_vgpu_get_dp_bitrate()
1023 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); in pri_surf_mmio_write()
1045 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in spr_surf_mmio_write()
1066 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1069 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1404 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, in sbi_data_mmio_read()
1572 vgpu->id); in pf_write()
1629 vgpu->id); in dma_ctrl_write()
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A Dgtt.c841 spt->vgpu = vgpu; in ppgtt_alloc_spt()
984 struct intel_vgpu *vgpu = spt->vgpu; in ppgtt_invalidate_pte() local
1001 struct intel_vgpu *vgpu = spt->vgpu; in ppgtt_invalidate_spt() local
1289 struct intel_vgpu *vgpu = spt->vgpu; in ppgtt_populate_spt() local
1324 struct intel_vgpu *vgpu = spt->vgpu; in ppgtt_handle_guest_entry_removal() local
1369 struct intel_vgpu *vgpu = spt->vgpu; in ppgtt_handle_guest_entry_add() local
1756 struct intel_vgpu *vgpu = mm->vgpu; in invalidate_ppgtt_mm() local
1786 struct intel_vgpu *vgpu = mm->vgpu; in shadow_ppgtt_mm() local
1838 mm->vgpu = vgpu; in vgpu_alloc_mm()
2043 struct intel_vgpu *vgpu = mm->vgpu; in ppgtt_get_next_level_entry() local
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A Dinterrupt.c201 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler()
204 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler()
243 vgpu_vreg(vgpu, reg) |= ier; in intel_vgpu_reg_master_irq_handler()
272 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler()
275 vgpu_vreg(vgpu, reg) = ier; in intel_vgpu_reg_ier_handler()
310 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler()
350 u32 val = vgpu_vreg(vgpu, in update_upstream_irq()
352 & vgpu_vreg(vgpu, in update_upstream_irq()
390 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); in update_upstream_irq()
454 if (vgpu->msi_trigger) in inject_virtual_interrupt()
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A Ddebugfs.c29 struct intel_vgpu *vgpu; member
87 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show()
89 .vgpu = vgpu, in vgpu_mmio_diff_show()
131 *val = vgpu->scan_nonprivbb; in vgpu_scan_nonprivbb_get()
146 vgpu->scan_nonprivbb = val; in vgpu_scan_nonprivbb_set()
179 vgpu->debugfs = debugfs_create_dir(name, vgpu->gvt->debugfs_root); in intel_gvt_debugfs_add_vgpu()
181 debugfs_create_file("mmio_diff", 0444, vgpu->debugfs, vgpu, in intel_gvt_debugfs_add_vgpu()
183 debugfs_create_file_unsafe("scan_nonprivbb", 0644, vgpu->debugfs, vgpu, in intel_gvt_debugfs_add_vgpu()
185 debugfs_create_file_unsafe("status", 0644, vgpu->debugfs, vgpu, in intel_gvt_debugfs_add_vgpu()
195 struct intel_gvt *gvt = vgpu->gvt; in intel_gvt_debugfs_remove_vgpu()
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A Dexeclist.c93 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_execlist_status() local
128 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_csb_update() local
162 intel_gvt_write_gpa(vgpu, in emulate_csb_update()
165 intel_gvt_write_gpa(vgpu, in emulate_csb_update()
184 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_execlist_ctx_schedule_out() local
257 struct intel_vgpu *vgpu = execlist->vgpu; in get_next_execlist_slot() local
282 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_execlist_schedule_in() local
372 struct intel_vgpu *vgpu = workload->vgpu; in prepare_execlist_workload() local
394 struct intel_vgpu *vgpu = workload->vgpu; in complete_execlist_workload() local
510 execlist->vgpu = vgpu; in init_vgpu_execlist()
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A Dpage_track.c35 struct intel_vgpu *vgpu, unsigned long gfn) in intel_vgpu_find_page_track() argument
37 return radix_tree_lookup(&vgpu->page_track_tree, gfn); in intel_vgpu_find_page_track()
56 track = intel_vgpu_find_page_track(vgpu, gfn); in intel_vgpu_register_page_track()
87 track = radix_tree_delete(&vgpu->page_track_tree, gfn); in intel_vgpu_unregister_page_track()
90 intel_gvt_page_track_remove(vgpu, gfn); in intel_vgpu_unregister_page_track()
108 track = intel_vgpu_find_page_track(vgpu, gfn); in intel_vgpu_enable_page_track()
115 ret = intel_gvt_page_track_add(vgpu, gfn); in intel_vgpu_enable_page_track()
135 track = intel_vgpu_find_page_track(vgpu, gfn); in intel_vgpu_disable_page_track()
142 ret = intel_gvt_page_track_remove(vgpu, gfn); in intel_vgpu_disable_page_track()
169 if (unlikely(vgpu->failsafe)) { in intel_vgpu_page_track_handler()
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A Ddmabuf.c49 struct intel_vgpu *vgpu; in vgpu_gem_get_pages() local
65 vgpu = fb_info->obj->vgpu; in vgpu_gem_get_pages()
120 struct intel_vgpu *vgpu = obj->vgpu; in vgpu_gem_put_pages() local
136 struct intel_vgpu *vgpu = obj->vgpu; in dmabuf_gem_object_free() local
140 if (vgpu && test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status) && in dmabuf_gem_object_free()
146 idr_remove(&vgpu->object_idr, in dmabuf_gem_object_free()
176 struct intel_vgpu *vgpu = obj->vgpu; in vgpu_gem_release() local
178 if (vgpu) { in vgpu_gem_release()
255 struct intel_vgpu *vgpu, in vgpu_get_plane_info() argument
467 dmabuf_obj->vgpu = vgpu; in intel_vgpu_query_plane()
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A Dfb_decoder.c194 if (pipe_is_enabled(vgpu, i)) in get_active_pipe()
216 pipe = get_active_pipe(vgpu); in intel_vgpu_decode_primary_plane()
255 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_primary_plane()
347 pipe = get_active_pipe(vgpu); in intel_vgpu_decode_cursor_plane()
378 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_cursor_plane()
426 pipe = get_active_pipe(vgpu); in intel_vgpu_decode_sprite_plane()
430 val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); in intel_vgpu_decode_sprite_plane()
482 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_sprite_plane()
495 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); in intel_vgpu_decode_sprite_plane()
503 val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); in intel_vgpu_decode_sprite_plane()
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A Dscheduler.c129 struct intel_vgpu *vgpu = workload->vgpu; in populate_shadow_context() local
363 struct intel_vgpu *vgpu = workload->vgpu; in copy_workload_to_ring_buffer() local
461 struct intel_vgpu *vgpu = workload->vgpu; in intel_gvt_workload_req_alloc() local
488 struct intel_vgpu *vgpu = workload->vgpu; in intel_gvt_scan_and_shadow_workload() local
686 struct intel_vgpu *vgpu = workload->vgpu; in intel_vgpu_shadow_mm_pin() local
739 struct intel_vgpu *vgpu = workload->vgpu; in prepare_workload() local
801 struct intel_vgpu *vgpu = workload->vgpu; in dispatch_workload() local
939 struct intel_vgpu *vgpu = workload->vgpu; in update_guest_context() local
1071 struct intel_vgpu *vgpu = workload->vgpu; in complete_current_workload() local
1202 vgpu = workload->vgpu; in workload_thread()
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A Ddisplay.h47 #define intel_vgpu_port(vgpu, port) \ argument
48 (&(vgpu->display.ports[port]))
50 #define intel_vgpu_has_monitor_on_port(vgpu, port) \ argument
51 (intel_vgpu_port(vgpu, port)->edid && \
52 intel_vgpu_port(vgpu, port)->edid->data_valid)
54 #define intel_vgpu_port_is_dp(vgpu, port) \ argument
55 ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
56 (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
57 (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
58 (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
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A Dgtt.h63 struct intel_vgpu *vgpu);
69 struct intel_vgpu *vgpu);
151 struct intel_vgpu *vgpu; member
218 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
219 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
221 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
243 struct intel_vgpu *vgpu; member
265 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);
267 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);
284 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
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A Dsched_policy.h43 int (*init_vgpu)(struct intel_vgpu *vgpu);
44 void (*clean_vgpu)(struct intel_vgpu *vgpu);
45 void (*start_schedule)(struct intel_vgpu *vgpu);
46 void (*stop_schedule)(struct intel_vgpu *vgpu);
55 int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu);
57 void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu);
59 void intel_vgpu_start_schedule(struct intel_vgpu *vgpu);
61 void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu);
A Dmmio.h83 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
84 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
85 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
87 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
89 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
91 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
94 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
96 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
102 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
105 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
A Dscheduler.h86 struct intel_vgpu *vgpu; member
134 #define workload_q_head(vgpu, e) \ argument
135 (&(vgpu)->submission.workload_q_head[(e)->id])
143 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
145 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu);
147 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
150 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu);
152 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
160 intel_vgpu_create_workload(struct intel_vgpu *vgpu,
166 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
A Dopregion.c220 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) in intel_vgpu_init_opregion() argument
227 gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); in intel_vgpu_init_opregion()
231 if (!vgpu_opregion(vgpu)->va) { in intel_vgpu_init_opregion()
237 buf = (u8 *)vgpu_opregion(vgpu)->va; in intel_vgpu_init_opregion()
275 vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; in intel_vgpu_opregion_base_write_handler()
284 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) in intel_vgpu_clean_opregion() argument
288 if (!vgpu_opregion(vgpu)->va) in intel_vgpu_clean_opregion()
292 free_pages((unsigned long)vgpu_opregion(vgpu)->va, in intel_vgpu_clean_opregion()
295 vgpu_opregion(vgpu)->va = NULL; in intel_vgpu_clean_opregion()
420 scic_pa = (vgpu_opregion(vgpu)->gfn[0] << PAGE_SHIFT) + in intel_vgpu_emulate_opregion_request()
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/linux/drivers/gpu/drm/i915/
A Dintel_gvt.c72 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; in free_initial_hw_state() local
74 vfree(vgpu->initial_mmio); in free_initial_hw_state()
75 vgpu->initial_mmio = NULL; in free_initial_hw_state()
77 kfree(vgpu->initial_cfg_space); in free_initial_hw_state()
78 vgpu->initial_cfg_space = NULL; in free_initial_hw_state()
107 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; in save_initial_hw_state() local
116 vgpu->initial_cfg_space = mem; in save_initial_hw_state()
127 vgpu->initial_mmio = mem; in save_initial_hw_state()
130 iter.data = vgpu->initial_mmio; in save_initial_hw_state()
140 vfree(vgpu->initial_mmio); in save_initial_hw_state()
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