| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
419 int vlevel, vlevel_max; in dcn301_fpu_calculate_wm_and_dlg() local
431 vlevel = 0; in dcn301_fpu_calculate_wm_and_dlg()
433 vlevel = vlevel_max; in dcn301_fpu_calculate_wm_and_dlg()
438 vlevel = min(max(vlevel_req, 2), vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
443 vlevel = min(max(vlevel_req, 1), vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
449 vlevel = min(vlevel_req, vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 279 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
1037 int vlevel) in subvp_validate_static_schedulability() argument
1397 unsigned int *vlevel, in try_odm_power_optimization_and_revalidate() argument
1438 int *vlevel, in dcn32_full_validate_bw_helper() argument
1492 vlevel_temp = *vlevel; in dcn32_full_validate_bw_helper()
1529 *vlevel = i; in dcn32_full_validate_bw_helper()
1543 *vlevel = i; in dcn32_full_validate_bw_helper()
2273 vlevel = i; in dcn32_internal_validate_bw()
2284 *vlevel_out = vlevel; in dcn32_internal_validate_bw()
2301 int vlevel) in dcn32_calculate_wm_and_dlg_fpu() argument
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| A D | dcn32_fpu.h | 57 int vlevel);
65 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
70 int vlevel,
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| A D | dcn20_fpu.c | 1145 int vlevel) in dcn20_calculate_dlg_params() argument
1735 int vlevel, in dcn20_calculate_wm() argument
1796 if (vlevel < 1) { in dcn20_calculate_wm()
1810 if (vlevel < 2) { in dcn20_calculate_wm()
1823 if (vlevel < 3) { in dcn20_calculate_wm()
2036 int vlevel = 0; in dcn20_validate_bandwidth_internal() local
2143 int vlevel, in dcn20_fpu_adjust_dppclk() argument
2245 int vlevel, vlevel_max; in dcn21_calculate_wm() local
2298 vlevel = 0; in dcn21_calculate_wm()
2300 vlevel = vlevel_max; in dcn21_calculate_wm()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 383 int vlevel) in dcn30_fpu_calculate_wm_and_dlg() argument
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
410 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
418 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true); in dcn30_fpu_calculate_wm_and_dlg()
428 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
437 if (vlevel == 0) { in dcn30_fpu_calculate_wm_and_dlg()
454 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
490 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn30_fpu_calculate_wm_and_dlg()
586 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
699 int vlevel) in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() argument
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| A D | dcn30_fpu.h | 50 int vlevel);
70 int vlevel);
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| /linux/drivers/soc/qcom/ |
| A D | spm.c | 333 unsigned int vlevel, volt_sel; in smp_set_vdd_v1_1() local
337 vlevel = volt_sel | 0x80; /* band */ in smp_set_vdd_v1_1()
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
365 sts, sts == vlevel, in smp_set_vdd_v1_1()
368 dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); in smp_set_vdd_v1_1()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.h | 73 int vlevel);
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| A D | dcn30_resource.c | 1639 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1670 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1687 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1690 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1697 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1870 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
1871 *vlevel_out = vlevel; in dcn30_internal_validate_bw()
2034 int vlevel) in dcn30_calculate_wm_and_dlg() argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1847 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1910 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1911 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1912 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1915 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1916 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
2029 return vlevel; in dcn20_validate_apply_pipe_split_flags()
2044 int pipe_cnt, i, pipe_idx, vlevel; in dcn20_fast_validate_bw() local
2065 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2068 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn20_fast_validate_bw()
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| A D | dcn20_resource.h | 129 int vlevel,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.h | 45 int vlevel);
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| A D | dcn31_fpu.c | 486 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
559 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.h | 47 int vlevel);
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| A D | dcn31_resource.c | 1728 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1731 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1764 int vlevel = 0; in dcn31_validate_bandwidth() local
1775 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true); in dcn31_validate_bandwidth()
1792 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 778 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
820 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
910 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 704 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) in dcn32_subvp_vblank_admissable() argument
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
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| A D | dcn32_resource.c | 1751 int vlevel = 0; in dml1_validate() local
1769 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dml1_validate()
1785 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
2013 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2016 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| A D | dcn32_resource.h | 114 int vlevel);
183 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);
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| /linux/arch/arm64/kvm/ |
| A D | arch_timer.c | 865 bool vlevel, plevel; in kvm_timer_should_notify_user() local
870 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
873 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 93 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1706 int vlevel = 0; in dcn314_validate_bandwidth() local
1718 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); in dcn314_validate_bandwidth()
1735 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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