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Searched refs:writel (Results 1 – 25 of 1991) sorted by relevance

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/linux/arch/arc/plat-hsdk/
A Dplatform.c232 writel(reg, CREG_AXI_M_HS_CORE_BOOT); in hsdk_init_memory_bridge()
275 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO)); in hsdk_init_memory_bridge()
276 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO)); in hsdk_init_memory_bridge()
277 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO)); in hsdk_init_memory_bridge()
281 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU)); in hsdk_init_memory_bridge()
282 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU)); in hsdk_init_memory_bridge()
283 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU)); in hsdk_init_memory_bridge()
284 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU)); in hsdk_init_memory_bridge()
285 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU)); in hsdk_init_memory_bridge()
301 writel(0x00000000, CREG_PAE); in hsdk_init_memory_bridge()
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_20nm.c22 writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, in dsi_20nm_dphy_set_timing()
39 writel(DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0), in dsi_20nm_dphy_set_timing()
86 writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0); in dsi_20nm_phy_enable()
104 writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3); in dsi_20nm_phy_enable()
107 writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0); in dsi_20nm_phy_enable()
108 writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1); in dsi_20nm_phy_enable()
109 writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2); in dsi_20nm_phy_enable()
110 writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4); in dsi_20nm_phy_enable()
114 writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1); in dsi_20nm_phy_enable()
120 writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0); in dsi_20nm_phy_enable()
[all …]
A Ddsi_phy_28nm.c109 writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); in pll_28nm_software_reset()
209 writel(0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG4); in dsi_pll_28nm_clk_set_rate()
307 writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); in _dsi_pll_28nm_vco_prepare_hpm()
311 writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); in _dsi_pll_28nm_vco_prepare_hpm()
315 writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); in _dsi_pll_28nm_vco_prepare_hpm()
730 writel(DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, in dsi_28nm_dphy_set_timing()
820 writel(0x00, base + REG_DSI_28nm_PHY_CTRL_1); in dsi_28nm_phy_enable()
821 writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0); in dsi_28nm_phy_enable()
837 writel(0, base + REG_DSI_28nm_PHY_LNCK_CFG_4); in dsi_28nm_phy_enable()
842 writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0); in dsi_28nm_phy_enable()
[all …]
A Ddsi_phy_28nm_8960.c112 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); in dsi_pll_28nm_clk_set_rate()
118 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_set_rate()
120 writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6); in dsi_pll_28nm_clk_set_rate()
124 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_clk_set_rate()
200 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_vco_prepare()
203 writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE, in dsi_pll_28nm_vco_prepare()
323 writel(val, bytediv->reg); in clk_bytediv_set_rate()
596 writel(0x5f, base + REG_DSI_28nm_8960_PHY_CTRL_0); in dsi_28nm_phy_enable()
597 writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_1); in dsi_28nm_phy_enable()
598 writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_2); in dsi_28nm_phy_enable()
[all …]
A Ddsi_phy_10nm.c190 writel(config->ssc_stepsize & 0xff, in dsi_pll_ssc_commit()
192 writel(config->ssc_stepsize >> 8, in dsi_pll_ssc_commit()
194 writel(config->ssc_div_per & 0xff, in dsi_pll_ssc_commit()
196 writel(config->ssc_div_per >> 8, in dsi_pll_ssc_commit()
198 writel(config->ssc_adj_per & 0xff, in dsi_pll_ssc_commit()
200 writel(config->ssc_adj_per >> 8, in dsi_pll_ssc_commit()
236 writel(config->decimal_div_start, in dsi_pll_commit()
238 writel(config->frac_div_start & 0xff, in dsi_pll_commit()
768 writel(tuning_cfg->rescode_offset_top[i], in dsi_phy_hw_v3_0_lane_settings()
770 writel(tuning_cfg->rescode_offset_bot[i], in dsi_phy_hw_v3_0_lane_settings()
[all …]
A Ddsi_phy_7nm.c209 writel(config->ssc_stepsize >> 8, in dsi_pll_ssc_commit()
211 writel(config->ssc_div_per & 0xff, in dsi_pll_ssc_commit()
213 writel(config->ssc_div_per >> 8, in dsi_pll_ssc_commit()
215 writel(config->ssc_adj_per & 0xff, in dsi_pll_ssc_commit()
217 writel(config->ssc_adj_per >> 8, in dsi_pll_ssc_commit()
292 writel(config->decimal_div_start, in dsi_pll_commit()
1001 writel(glbl_str_swi_cal_sel_ctrl, in dsi_7nm_phy_enable()
1003 writel(glbl_hstx_str_ctrl_0, in dsi_7nm_phy_enable()
1005 writel(glbl_pemph_ctrl_0, in dsi_7nm_phy_enable()
1009 writel(glbl_rescode_top_ctrl, in dsi_7nm_phy_enable()
[all …]
A Ddsi_phy_14nm.c298 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1); in pll_db_commit_ssc()
301 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2); in pll_db_commit_ssc()
328 writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN); in pll_db_commit_common()
346 writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1); in pll_db_commit_common()
348 writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM); in pll_db_commit_common()
350 writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM); in pll_db_commit_common()
362 writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM); in pll_db_commit_common()
381 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); in pll_14nm_software_reset()
976 writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06, in dsi_14nm_phy_enable()
979 writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f, in dsi_14nm_phy_enable()
[all …]
/linux/drivers/phy/qualcomm/
A Dphy-qcom-edp.c229 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
369 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v4()
544 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v6()
755 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
768 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
769 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
770 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
771 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
777 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
822 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
[all …]
/linux/drivers/video/fbdev/via/
A Daccel.c91 writel(tmp, engine + 0x08); in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
124 writel(tmp, engine + 0x30); in hw_bitblt_1()
133 writel(tmp, engine + 0x34); in hw_bitblt_1()
145 writel(tmp, engine + 0x38); in hw_bitblt_1()
158 writel(ge_cmd, engine); in hw_bitblt_1()
226 writel(tmp, engine + 0x08); in hw_bitblt_2()
234 writel(tmp, engine + 0x0C); in hw_bitblt_2()
290 writel(ge_cmd, engine); in hw_bitblt_2()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_reg.c245 writel(reg, dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
271 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
291 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
301 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
311 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
330 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
337 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
340 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
343 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
[all …]
/linux/drivers/video/fbdev/
A Dwmt_ge_rops.c62 writel(p->var.bits_per_pixel == 32 ? 3 : in wmt_ge_fillrect()
73 writel(pat, regbase + GE_PAT0C_OFF); in wmt_ge_fillrect()
74 writel(1, regbase + GE_COMMAND_OFF); in wmt_ge_fillrect()
76 writel(1, regbase + GE_FIRE_OFF); in wmt_ge_fillrect()
88 writel(p->var.bits_per_pixel > 16 ? 3 : in wmt_ge_copyarea()
94 writel(area->sx, regbase + GE_SRCAREAX_OFF); in wmt_ge_copyarea()
95 writel(area->sy, regbase + GE_SRCAREAY_OFF); in wmt_ge_copyarea()
107 writel(0xcc, regbase + GE_ROPCODE_OFF); in wmt_ge_copyarea()
108 writel(1, regbase + GE_COMMAND_OFF); in wmt_ge_copyarea()
109 writel(1, regbase + GE_FIRE_OFF); in wmt_ge_copyarea()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
A Despi.c56 writel(V_WRITE_DATA(wr_data) | in tricn_write()
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
102 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init()
182 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_pm3393()
183 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_pm3393()
184 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_pm3393()
234 writel(0, adapter->regs + A_ESPI_TRAIN); in t1_espi_init()
237 writel(V_OUT_OF_SYNC_COUNT(4) | in t1_espi_init()
240 writel(nports == 4 ? 0x200040 : 0x1000080, in t1_espi_init()
255 writel(status_enable_extra | F_RXSTATUSENABLE, in t1_espi_init()
[all …]
A Dtp.c32 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init()
33 writel(F_TP_OUT_CSPI_CPL | in tp_init()
37 writel(V_IP_TTL(64) | in tp_init()
47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init()
78 writel(0xffffffff, in t1_tp_intr_enable()
80 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable()
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
87 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable()
100 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable()
106 writel(tp_intr & ~F_PL_INTR_TP, in t1_tp_intr_disable()
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
A Djpeg-hw-exynos3250.c23 writel(1, regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
35 writel(1, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
41 writel(0, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
222 writel(reg, regs + EXYNOS3250_JPGY); in exynos3250_jpeg_set_y()
230 writel(reg, regs + EXYNOS3250_JPGX); in exynos3250_jpeg_set_x()
393 writel(EXYNOS3250_JPEG_ENC_COEF1, in exynos3250_jpeg_coef()
395 writel(EXYNOS3250_JPEG_ENC_COEF2, in exynos3250_jpeg_coef()
397 writel(EXYNOS3250_JPEG_ENC_COEF3, in exynos3250_jpeg_coef()
400 writel(EXYNOS3250_JPEG_DEC_COEF1, in exynos3250_jpeg_coef()
402 writel(EXYNOS3250_JPEG_DEC_COEF2, in exynos3250_jpeg_coef()
[all …]
A Djpeg-hw-exynos4.c39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
47 writel(reg & EXYNOS4_ENC_DEC_MODE_MASK, in exynos4_jpeg_set_enc_dec_mode()
133 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_img_fmt()
166 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_enc_out_fmt()
200 writel(reg | EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
203 writel(reg & ~EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
252 writel(reg, base + EXYNOS4_TBL_SEL_REG); in exynos4_jpeg_set_encode_tbl_select()
262 writel(reg, base + EXYNOS4_TBL_SEL_REG); in exynos4_jpeg_set_dec_components()
272 writel(reg, base + EXYNOS4_TBL_SEL_REG); in exynos4_jpeg_select_dec_q_tbl()
[all …]
/linux/drivers/ata/
A Dahci_qoriq.c134 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
138 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
174 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); in ahci_qoriq_phy_init()
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
182 writel(AHCI_PORT_AXICC_CFG, in ahci_qoriq_phy_init()
190 writel(readl(qpriv->ecc_addr) | in ahci_qoriq_phy_init()
214 writel(readl(qpriv->ecc_addr) | in ahci_qoriq_phy_init()
[all …]
/linux/drivers/scsi/bfa/
A Dbfa_ioc_ct.c66 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
69 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
137 writel(~0U, ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
364 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
569 writel(r32 & __MSIX_VT_OFST_, in bfa_ioc_ct2_poweron()
597 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
633 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
643 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
739 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
744 writel(0, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
[all …]
/linux/drivers/net/ethernet/brocade/bna/
A Dbfa_ioc_ct.c452 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron()
616 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
617 writel(__APP_EMS_CMLCKSEL | in bfa_ioc_ct_pll_init()
623 writel(__APP_EMS_REFCKBUFEN1, in bfa_ioc_ct_pll_init()
634 writel(pll_sclk | in bfa_ioc_ct_pll_init()
637 writel(pll_fclk | in bfa_ioc_ct_pll_init()
640 writel(pll_sclk | in bfa_ioc_ct_pll_init()
643 writel(pll_fclk | in bfa_ioc_ct_pll_init()
650 writel(pll_sclk | in bfa_ioc_ct_pll_init()
653 writel(pll_fclk | in bfa_ioc_ct_pll_init()
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
A Ds5p_mfc_opr_v6.c35 #undef writel
36 #define writel(v, r) \ macro
988 writel(p->rc_bitrate, in s5p_mfc_set_enc_params()
998 writel(1, mfc_regs->e_rc_mode); in s5p_mfc_set_enc_params()
1001 writel(0, mfc_regs->e_rc_mode); in s5p_mfc_set_enc_params()
1004 writel(2, mfc_regs->e_rc_mode); in s5p_mfc_set_enc_params()
1008 writel(1, mfc_regs->e_rc_mode); in s5p_mfc_set_enc_params()
1149 writel(ctx->img_height >> 1, in s5p_mfc_set_enc_params_h264()
1152 writel(ctx->img_height >> 1, in s5p_mfc_set_enc_params_h264()
1324 writel(p_h264->fmo_chg_rate, in s5p_mfc_set_enc_params_h264()
[all …]
/linux/sound/soc/pxa/
A Dpxa2xx-i2s.c103 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_startup()
175 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
189 writel(0x48, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
192 writel(0x34, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
195 writel(0x24, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
198 writel(0x1a, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
201 writel(0xd, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
204 writel(0xc, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
207 writel(0x6, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
307 writel(SACR0_RST, i2s_reg_base + SACR0); in pxa2xx_i2s_probe()
[all …]
/linux/sound/soc/ux500/
A Dux500_msp_i2s.c295 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
297 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
299 writel(mcfg->tx_channel_2_enable, in configure_multichannel()
301 writel(mcfg->tx_channel_3_enable, in configure_multichannel()
316 writel(mcfg->rx_channel_0_enable, in configure_multichannel()
318 writel(mcfg->rx_channel_1_enable, in configure_multichannel()
332 writel(reg_val_MCR | in configure_multichannel()
336 writel(mcfg->comparison_mask, in configure_multichannel()
338 writel(mcfg->comparison_value, in configure_multichannel()
493 writel(reg_val_IMSC & in disable_msp_rx()
[all …]
/linux/drivers/net/ethernet/sunplus/
A Dspl2sw_mac.c28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_add()
105 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_del()
131 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
155 writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0); in spl2sw_mac_hw_init()
166 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
176 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_init()
[all …]
/linux/arch/m68k/coldfire/
A Dm53xx.c317 writel(0x77777777, MCF_SCM_MPR); in scm_init()
321 writel(0, MCF_SCM_PACRA); in scm_init()
322 writel(0, MCF_SCM_PACRB); in scm_init()
323 writel(0, MCF_SCM_PACRC); in scm_init()
324 writel(0, MCF_SCM_PACRD); in scm_init()
325 writel(0, MCF_SCM_PACRE); in scm_init()
326 writel(0, MCF_SCM_PACRF); in scm_init()
348 writel(MCF_FBCS_CSCR_PS_16 | in fbcs_init()
357 writel(MCF_FBCS_CSCR_PS_16 | in fbcs_init()
401 writel(MCF_SDRAMC_SDCR_MODE_EN | in sdramc_init()
[all …]
/linux/drivers/video/fbdev/geode/
A Ddisplay_gx1.c93 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
100 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
131 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode()
162 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode()
164 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode()
166 writel(val, par->dc_regs + DC_H_TIMING_3); in gx1_set_mode()
169 writel(val, par->dc_regs + DC_V_TIMING_1); in gx1_set_mode()
171 writel(val, par->dc_regs + DC_V_TIMING_2); in gx1_set_mode()
173 writel(val, par->dc_regs + DC_V_TIMING_3); in gx1_set_mode()
186 writel(0, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
[all …]
/linux/drivers/net/hippi/
A Drrunner.c305 writel(0, &regs->Timer); in rr_reset()
359 writel(0, &regs->Event); in rr_reset()
361 writel(0, &regs->TxPi); in rr_reset()
362 writel(0, &regs->IpRxPi); in rr_reset()
364 writel(0, &regs->EvtCon); in rr_reset()
365 writel(0, &regs->EvtPrd); in rr_reset()
409 writel(0, &regs->ExtIo); in rr_read_eeprom()
425 writel(io, &regs->ExtIo); in rr_read_eeprom()
461 writel(0, &regs->ExtIo); in write_eeprom()
497 writel(io, &regs->ExtIo); in write_eeprom()
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