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Searched refs:wrmsrl (Results 1 – 25 of 83) sorted by relevance

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/linux/arch/x86/kernel/
A Dfred.c46 wrmsrl(MSR_IA32_FRED_CONFIG, in cpu_init_fred_exceptions()
52 wrmsrl(MSR_IA32_FRED_STKLVLS, 0); in cpu_init_fred_exceptions()
53 wrmsrl(MSR_IA32_FRED_RSP0, 0); in cpu_init_fred_exceptions()
54 wrmsrl(MSR_IA32_FRED_RSP1, 0); in cpu_init_fred_exceptions()
55 wrmsrl(MSR_IA32_FRED_RSP2, 0); in cpu_init_fred_exceptions()
56 wrmsrl(MSR_IA32_FRED_RSP3, 0); in cpu_init_fred_exceptions()
76 wrmsrl(MSR_IA32_FRED_STKLVLS, in cpu_init_fred_rsps()
83 wrmsrl(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); in cpu_init_fred_rsps()
84 wrmsrl(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); in cpu_init_fred_rsps()
85 wrmsrl(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); in cpu_init_fred_rsps()
A Dkvm.c304 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
366 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
379 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
391 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
454 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
456 wrmsrl(MSR_KVM_MIGRATION_CONTROL, 0); in kvm_guest_cpu_offline()
618 wrmsrl(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); in setup_efi_kvm_sev_migration()
743 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_resume()
979 wrmsrl(MSR_KVM_MIGRATION_CONTROL, in kvm_init_platform()
1128 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_disable_host_haltpoll()
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A Dshstk.c176 wrmsrl(MSR_IA32_PL3_SSP, addr + size); in shstk_setup()
177 wrmsrl(MSR_IA32_U_CET, CET_SHSTK_EN); in shstk_setup()
375 wrmsrl(MSR_IA32_PL3_SSP, ssp); in setup_signal_shadow_stack()
399 wrmsrl(MSR_IA32_PL3_SSP, ssp); in restore_signal_shadow_stack()
476 wrmsrl(MSR_IA32_U_CET, msrval); in wrss_control()
495 wrmsrl(MSR_IA32_U_CET, 0); in shstk_disable()
496 wrmsrl(MSR_IA32_PL3_SSP, 0); in shstk_disable()
A Dtsc_sync.c73 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
145 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
232 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
521 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
A Dprocess.c341 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); in set_cpuid_faulting()
558 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
575 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
585 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
594 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
604 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); in amd_set_ssb_virt_state()
711 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __switch_to_xtra()
/linux/arch/x86/hyperv/
A Dhv_init.c135 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_init()
261 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_die()
340 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
524 wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); in hyperv_init()
635 wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); in hyperv_init()
656 wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); in hyperv_cleanup()
696 wrmsrl(HV_X64_MSR_CRASH_P0, err); in hyperv_report_panic()
697 wrmsrl(HV_X64_MSR_CRASH_P1, guest_id); in hyperv_report_panic()
698 wrmsrl(HV_X64_MSR_CRASH_P2, regs->ip); in hyperv_report_panic()
699 wrmsrl(HV_X64_MSR_CRASH_P3, regs->ax); in hyperv_report_panic()
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/linux/arch/x86/events/intel/
A Duncore_nhmex.c208 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
222 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
237 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
243 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
385 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
386 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
470 wrmsrl(reg1->reg, 0); in nhmex_sbox_msr_enable_event()
471 wrmsrl(reg1->reg + 1, reg1->config); in nhmex_sbox_msr_enable_event()
472 wrmsrl(reg1->reg + 2, reg2->config); in nhmex_sbox_msr_enable_event()
853 wrmsrl(reg2->reg, 0); in nhmex_mbox_msr_enable_event()
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A Duncore_snb.c265 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
270 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
276 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box()
283 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_enable_box()
290 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box()
375 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_init_box()
386 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_enable_box()
393 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box()
555 wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); in adl_uncore_msr_disable_box()
561 wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); in adl_uncore_msr_exit_box()
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A Dlbr.c140 wrmsrl(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable()
158 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable()
169 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
177 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
178 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
180 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
202 wrmsrl(MSR_LBR_SELECT, 0); in intel_pmu_lbr_reset()
285 wrmsrl(x86_pmu.lbr_from + idx, val); in wrlbr_from()
290 wrmsrl(x86_pmu.lbr_to + idx, val); in wrlbr_to()
295 wrmsrl(x86_pmu.lbr_info + idx, val); in wrlbr_info()
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A Dknc.c164 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all()
173 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all()
210 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
A Dp6.c145 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
155 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
A Duncore_discovery.c444 wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); in intel_generic_uncore_msr_init_box()
449 wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); in intel_generic_uncore_msr_disable_box()
454 wrmsrl(intel_generic_uncore_box_ctl(box), 0); in intel_generic_uncore_msr_enable_box()
462 wrmsrl(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
470 wrmsrl(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
/linux/arch/x86/kernel/cpu/
A Dtsx.c40 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
59 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
120 wrmsrl(MSR_TSX_FORCE_ABORT, msr); in tsx_clear_cpuid()
124 wrmsrl(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
153 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); in tsx_dev_mode_disable()
A Dcommon.c581 wrmsrl(MSR_IA32_S_CET, msr); in ibt_restore()
607 wrmsrl(MSR_IA32_S_CET, 0); in setup_cet()
613 wrmsrl(MSR_IA32_S_CET, 0); in setup_cet()
624 wrmsrl(MSR_IA32_S_CET, 0); in cet_disable()
625 wrmsrl(MSR_IA32_U_CET, 0); in cet_disable()
1707 wrmsrl(MSR_FS_BASE, 1); in detect_null_seg_behavior()
1710 wrmsrl(MSR_FS_BASE, old_base); in detect_null_seg_behavior()
2033 wrmsrl(MSR_CSTAR, val); in wrmsrl_cstar()
2063 wrmsrl(MSR_SYSCALL_MASK, in idt_syscall_init()
2250 wrmsrl(MSR_FS_BASE, 0); in cpu_init()
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/linux/arch/x86/kernel/cpu/mce/
A Dinject.c479 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
483 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
484 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
486 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
487 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
490 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
493 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
495 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
496 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
499 wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); in prepare_msrs()
A Dintel.c145 wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
234 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_claim_bank()
328 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
435 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
447 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/linux/arch/x86/power/
A Dcpu.c58 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
210 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
233 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
256 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
/linux/arch/x86/events/amd/
A Dlbr.c64 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2, val); in amd_pmu_lbr_set_from()
69 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); in amd_pmu_lbr_set_to()
336 wrmsrl(MSR_AMD64_LBR_SELECT, 0); in amd_pmu_lbr_reset()
398 wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select); in amd_pmu_lbr_enable_all()
403 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_enable_all()
407 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_enable_all()
/linux/arch/x86/xen/
A Dsuspend.c42 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
60 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
/linux/drivers/video/fbdev/geode/
A Dvideo_gx.c154 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
162 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); in gx_set_dclk_frequency()
166 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
186 wrmsrl(MSR_GX_MSR_PADSEL, val); in gx_configure_tft()
/linux/drivers/cpufreq/
A Dlonghaul.c147 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
156 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
197 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
215 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
234 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
/linux/drivers/platform/x86/intel/ifs/
A Dload.c130 wrmsrl(msrs->copy_hashes, ifs_hash_ptr); in copy_hashes_authenticate_chunks()
152 wrmsrl(msrs->copy_chunks, linear_addr); in copy_hashes_authenticate_chunks()
198 wrmsrl(msrs->copy_hashes, ifs_hash_ptr); in copy_hashes_authenticate_chunks_gen2()
219 wrmsrl(msrs->test_ctrl, INVALIDATE_STRIDE); in copy_hashes_authenticate_chunks_gen2()
241 wrmsrl(msrs->copy_chunks, (u64)chunk_table); in copy_hashes_authenticate_chunks_gen2()
/linux/arch/x86/events/zhaoxin/
A Dcore.c257 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); in zhaoxin_pmu_disable_all()
262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
276 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in zhaoxin_pmu_ack_status()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
/linux/drivers/platform/x86/intel/speed_select_if/
A Disst_if_mbox_msr.c55 wrmsrl(MSR_OS_MAILBOX_DATA, command_data); in isst_if_send_mbox_cmd()
62 wrmsrl(MSR_OS_MAILBOX_INTERFACE, data); in isst_if_send_mbox_cmd()
/linux/arch/x86/events/
A Dperf_event.h1196 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); in __x86_pmu_enable_event()
1203 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); in __x86_pmu_enable_event()
1205 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
1221 wrmsrl(hwc->config_base, hwc->config & ~disable_mask); in x86_pmu_disable_event()
1224 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); in x86_pmu_disable_event()
1392 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); in __amd_pmu_lbr_disable()
1396 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in __amd_pmu_lbr_disable()
1526 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); in __intel_pmu_pebs_disable_all()
1531 wrmsrl(MSR_ARCH_LBR_CTL, 0); in __intel_pmu_arch_lbr_disable()
1540 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_disable()

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