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Searched refs:xcc_mask (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfxhub_v1_2.c68 uint32_t xcc_mask; in gfxhub_v1_2_setup_vm_pt_regs() local
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
125 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_system_aperture_regs() argument
431 uint32_t xcc_mask; in gfxhub_v1_2_gart_enable() local
433 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_enable()
472 uint32_t xcc_mask; in gfxhub_v1_2_gart_disable() local
474 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_disable()
530 uint32_t xcc_mask; in gfxhub_v1_2_set_fault_enable_default() local
532 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_set_fault_enable_default()
579 uint32_t xcc_mask; in gfxhub_v1_2_init() local
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A Daqua_vanjaram.c279 { GC_HWIP, adev->gfx.xcc_mask }, in aqua_vanjaram_ip_map_init()
317 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_calc_xcp_mode()
369 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()
405 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; in __aqua_vanjaram_get_xcp_ip_info()
456 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()
480 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()
541 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_switch_partition_mode()
603 uint32_t xcc_mask; in aqua_vanjaram_get_xcp_mem_id() local
620 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); in aqua_vanjaram_get_xcp_mem_id()
621 if (r || !xcc_mask) in aqua_vanjaram_get_xcp_mem_id()
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A Dgfx_v9_4_3.c337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
630 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_mec_init()
808 NUM_XCC(adev->gfx.xcc_mask) / in gfx_v9_4_3_switch_compute_partition()
1028 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_alloc_ip_dump()
1080 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_init()
1189 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_fini()
1328 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_constants_init()
1407 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1500 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_rlc_stop()
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A Damdgpu_gfx.c218 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
1002 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
1003 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); in amdgpu_gfx_ras_error_func() local
1011 for_each_inst(i, xcc_mask) in amdgpu_gfx_ras_error_func()
1330 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()
1375 switch (NUM_XCC(adev->gfx.xcc_mask)) { in amdgpu_gfx_get_available_compute_partition()
1446 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_run_cleaner_shader()
A Dta_ras_if.h140 uint16_t xcc_mask; member
A Dgmc_v9_0.c1864 uint32_t xcc_mask; in gmc_v9_0_init_acpi_mem_ranges() local
1866 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gmc_v9_0_init_acpi_mem_ranges()
1867 xcc_mask = (1U << num_xcc) - 1; in gmc_v9_0_init_acpi_mem_ranges()
1869 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
2091 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
A Damdgpu_virt.c1020 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
A Damdgpu_vm.h504 uint32_t xcc_mask);
A Damdgpu_gfx.h451 uint16_t xcc_mask; member
A Dnbio_v7_9.c426 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
A Damdgpu_discovery.c712 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1002 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1293 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1388 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
A Dsdma_v4_4_2.c141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
A Damdgpu_vm.c1570 uint32_t xcc_mask) in amdgpu_vm_flush_compute_tlb() argument
1590 for_each_inst(xcc, xcc_mask) { in amdgpu_vm_flush_compute_tlb()
A Damdgpu_psp.c1807 ras_cmd->ras_in_message.init_flags.xcc_mask = in psp_ras_initialize()
1808 adev->gfx.xcc_mask; in psp_ras_initialize()
A Damdgpu_ras.c359 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_ras_instance_mask_check()
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_mqd_manager_v9.c140 NUM_XCC(node->xcc_mask), in allocate_mqd()
571 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
576 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
595 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
601 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
621 uint32_t xcc_mask = mm->dev->xcc_mask; in check_preemption_failed_v9_4_3() local
626 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
688 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v9_4_3()
751 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_mqd_v9_4_3() local
760 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
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A Dkfd_mqd_manager.c80 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()
109 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
110 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask()
A Dkfd_device_queue_manager.c144 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
147 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
485 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_trap_handler_settings() local
489 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
758 uint32_t xcc_mask = dev->xcc_mask; in dbgdev_wave_reset_wavefronts() local
804 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
1429 uint32_t xcc_mask = dqm->dev->xcc_mask; in set_pasid_vmid_mapping() local
1432 for_each_inst(xcc_id, xcc_mask) { in set_pasid_vmid_mapping()
1444 uint32_t xcc_mask = dqm->dev->xcc_mask; in init_interrupts() local
2781 NUM_XCC(dqm->dev->xcc_mask)); in allocate_hiq_sdma_mqd()
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A Dkfd_queue.c299 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_acquire_buffers()
346 * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_release_buffers()
429 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); in kfd_queue_ctx_save_restore_size()
A Dkfd_device.c653 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
676 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
836 &node->xcc_mask); in kgd2kfd_device_init()
839 node->xcc_mask = in kgd2kfd_device_init()
840 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
A Dkfd_debug.c450 uint32_t xcc_mask = pdd->dev->xcc_mask; in kfd_dbg_trap_set_dev_address_watch() local
464 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
1081 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
A Dkfd_topology.c481 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
547 NUM_XCC(dev->gpu->xcc_mask)); in node_show()
1118 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()
1689 int num_xcc = NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()
1694 start = ffs(knode->xcc_mask) - 1; in fill_in_l2_l3_pcache()
1804 start = ffs(kdev->xcc_mask) - 1; in kfd_fill_cache_non_crat_info()
1805 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
A Dkfd_priv.h271 uint32_t xcc_mask; /* Instance mask of XCCs present */ member
1504 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); in kfd_flush_tlb()
A Dkfd_process.c304 &max_waves_per_cu, ffs(dev->xcc_mask) - 1); in kfd_get_cu_occupancy()
314 wave_cnt += (NUM_XCC(dev->xcc_mask) * in kfd_get_cu_occupancy()
A Dkfd_process_queue_manager.c1105 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()

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