Searched refs:CONTROL (Results 1 – 11 of 11) sorted by relevance
| /qemu/include/hw/rtc/ |
| A D | xlnx-zynqmp-rtc.h | 72 REG32(CONTROL, 0x40)
73 FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
74 FIELD(CONTROL, OSC_CNTRL, 24, 4)
75 FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
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| /qemu/hw/rtc/ |
| A D | aspeed_rtc.c | 21 #define CONTROL (0x10 / 4) macro
78 if (rtc->reg[CONTROL] & RTC_ENABLED) { in aspeed_rtc_read()
82 case CONTROL: in aspeed_rtc_read()
106 if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) { in aspeed_rtc_write()
110 case CONTROL: in aspeed_rtc_write()
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| /qemu/hw/timer/ |
| A D | cmsdk-apb-dualtimer.c | 35 FIELD(CONTROL, ONESHOT, 0, 1)
36 FIELD(CONTROL, SIZE, 1, 1)
37 FIELD(CONTROL, PRESCALE, 2, 2)
38 FIELD(CONTROL, INTEN, 5, 1)
39 FIELD(CONTROL, MODE, 6, 1)
40 FIELD(CONTROL, ENABLE, 7, 1)
112 switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_divisor()
145 switch (FIELD_EX32(newctrl, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_write_control()
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| /qemu/hw/ssi/ |
| A D | ibex_spi_host.c | 48 REG32(CONTROL, 0x10)
49 FIELD(CONTROL, RX_WATERMARK, 0, 8)
50 FIELD(CONTROL, TX_WATERMARK, 1, 8)
51 FIELD(CONTROL, OUTPUT_EN, 29, 1)
52 FIELD(CONTROL, SW_RST, 30, 1)
53 FIELD(CONTROL, SPIEN, 31, 1)
416 CONTROL, SPIEN))) { in ibex_spi_host_write()
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| /qemu/target/hexagon/idef-parser/ |
| A D | idef-parser.h | 45 typedef enum { GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW } HexRegType; enumerator
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| A D | parser-helpers.c | 130 case CONTROL: in reg_compose()
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| /qemu/scripts/qapi/ |
| A D | pylintrc | 3 [MESSAGES CONTROL]
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| /qemu/tests/qemu-iotests/ |
| A D | pylintrc | 1 [MESSAGES CONTROL]
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| /qemu/migration/ |
| A D | trace-events | 223 qemu_rdma_exchange_get_response_start(const char *desc) "CONTROL: %s receiving..."
233 qemu_rdma_post_send_control(const char *desc) "CONTROL: sending %s.."
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| /qemu/target/s390x/tcg/ |
| A D | insn-data.h.inc | 1346 /* LOAD CONTROL */
1372 /* SET ADDRESS SPACE CONTROL FAST */
1394 /* STORE CONTROL */
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| /qemu/docs/specs/ |
| A D | rocker.rst | 459 CONTROL: offset 0x0300, 32-bit, (W)
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