Home
last modified time | relevance | path

Searched refs:IOAPIC_NUM_PINS (Results 1 – 14 of 14) sorted by relevance

/qemu/hw/intc/
A Dioapic_internal.h105 uint64_t ioredtbl[IOAPIC_NUM_PINS];
108 uint64_t irq_count[IOAPIC_NUM_PINS];
109 int irq_level[IOAPIC_NUM_PINS];
110 int irq_eoi[IOAPIC_NUM_PINS];
A Dioapic_common.c56 *nb_irqs = IOAPIC_NUM_PINS; in ioapic_get_statistics()
70 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_irr_dump()
93 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_print_redtbl()
127 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_reset_common()
195 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS),
A Dioapic.c99 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_service()
166 if (vector < IOAPIC_NUM_PINS) { in ioapic_set_irq()
198 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_update_kvm_routes()
236 for (n = 0; n < IOAPIC_NUM_PINS; n++) { in ioapic_eoi_broadcast()
319 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); in ioapic_mem_read()
323 if (index >= 0 && index < IOAPIC_NUM_PINS) { in ioapic_mem_read()
394 if (index >= 0 && index < IOAPIC_NUM_PINS) { in ioapic_mem_write()
465 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); in ioapic_realize()
/qemu/hw/i386/kvm/
A Dioapic.c74 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in kvm_ioapic_get()
92 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in kvm_ioapic_put()
133 qdev_init_gpio_in(dev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS); in kvm_ioapic_realize()
A Dxen_evtchn.c164 uint16_t gsi_pirq[IOAPIC_NUM_PINS];
226 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in xen_evtchn_post_load()
263 VMSTATE_UINT16_ARRAY(gsi_pirq, XenEvtchnState, IOAPIC_NUM_PINS),
1566 for (pirq = 16 ; pirq < IOAPIC_NUM_PINS; pirq++) { in allocate_pirq()
1575 for (pirq = s->nr_pirqs - 1; pirq >= IOAPIC_NUM_PINS; pirq--) { in allocate_pirq()
1592 assert(gsi < IOAPIC_NUM_PINS); in allocate_pirq()
1606 if (!s || gsi < 0 || gsi >= IOAPIC_NUM_PINS) { in xen_evtchn_set_gsi()
1836 if (gsi < 0 || gsi >= IOAPIC_NUM_PINS) { in xen_physdev_map_pirq()
/qemu/include/hw/i386/
A Dx86.h147 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
148 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
/qemu/include/hw/intc/
A Dioapic.h23 #define IOAPIC_NUM_PINS 24 macro
/qemu/include/hw/southbridge/
A Dich9.h70 qemu_irq gsi[IOAPIC_NUM_PINS];
/qemu/hw/i386/
A Dx86-common.c462 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: in gsi_handler()
477 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: in gsi_handler()
500 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_init_gsi()
516 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in ioapic_init_secondary()
A Dmicrovm.c172 IOAPIC_NUM_PINS * ioapics); in microvm_devices_init()
193 mms->virtio_num_transports = IOAPIC_NUM_PINS; in microvm_devices_init()
A Dpc.c294 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); in pc_gsi_create()
1184 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in pc_basic_device_init()
1201 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); in pc_basic_device_init()
A Dpc_q35.c238 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in pc_q35_init()
/qemu/hw/isa/
A Dlpc_ich9.c688 IOAPIC_NUM_PINS); in ich9_lpc_initfn()
/qemu/target/i386/kvm/
A Dkvm.c6145 for (i = 0; i < IOAPIC_NUM_PINS; i++) { in kvm_arch_init_irq_routing()

Completed in 59 milliseconds