Searched refs:Interrupt (Results 1 – 25 of 42) sorted by relevance
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| /qemu/rust/hw/char/pl011/src/ |
| A D | device.rs | 20 registers::{self, Interrupt},
381 il &= !Interrupt::MS; in loopback_mdmctrl()
531 Interrupt::E
532 | Interrupt::MS
533 | Interrupt::RT as u32
534 | Interrupt::TX as u32
536 Interrupt::RX as u32,
537 Interrupt::TX as u32,
538 Interrupt::RT as u32,
539 Interrupt::MS,
[all …]
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| A D | lib.rs | 568 pub enum Interrupt { enum
582 impl Interrupt { implementation
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| /qemu/docs/specs/ |
| A D | ppc-xive.rst | 6 architecture, called XIVE as "eXternal Interrupt Virtualization
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
39 XIVE Interrupt Controller
137 - Interrupt Priority Register (PIPR)
138 - Interrupt Pending Buffer (IPB)
145 The Thread Interrupt Management registers are accessible through a
146 specific MMIO region, called the Thread Interrupt Management Area
155 Interrupt flow from an O/S perspective
[all …]
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| A D | pci-serial.rst | 22 Interrupt:
36 Interrupt:
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| A D | ivshmem-spec.rst | 64 0 4 read/write 0 Interrupt Mask
68 4 4 read/write 0 Interrupt Status
82 In revision 0 of the device, Interrupt Status and Mask Register
85 Mask is non-zero and the device has no MSI-X capability. Interrupt
119 Interrupt Status register is set to 1. This asserts INTx unless
120 masked by the Interrupt Mask register. The device is not capable to
127 Interrupt infrastructure
207 5. Interrupt setup. This is the client's own ID, repeated N times.
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| A D | acpi_hw_reduced_hotplug.rst | 29 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
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| A D | rocker.rst | 69 0x3C 1 Interrupt line
70 0x3D 1 Interrupt pin 0x00
150 Software should install the Interrupt Service Routine (ISR) before any ports
279 Interrupt credits
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| /qemu/target/ppc/ |
| A D | power8-pmu-regs.c.inc | 20 * Facility Unavailable Interrupt will occur.
38 * Assistance Interrupt. Userspace writing with PMCC 0b01 will
39 * generate a Facility Unavailable Interrupt.
205 * Interrupt.
238 * Interrupt.
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| /qemu/docs/system/arm/ |
| A D | collie.rst | 10 * Interrupt controller
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| A D | raspi.rst | 22 * Interrupt controller
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| A D | realview.rst | 17 - Arm AMBA Generic/Distributed Interrupt Controller
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| A D | versatile.rst | 8 - PL190 Vectored Interrupt Controller
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| A D | sabrelite.rst | 14 * Generic Interrupt Controller
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| A D | aspeed.rst | 51 * Interrupt Controller (VIC)
291 * Interrupt Controller (VIC)
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| A D | bananapi_m2u.rst | 16 * Generic Interrupt Controller configuration
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| /qemu/docs/system/openrisc/ |
| A D | cpu-features.rst | 10 - Programmable Interrupt Controller (PIC)
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| /qemu/docs/system/ |
| A D | target-rx.rst | 12 - Interrupt Control Unit (ICUa)
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| A D | cpu-hotplug.rst | 138 Interrupt (SCI) and calls the ACPI handler for the affected vCPU
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| /qemu/hw/riscv/ |
| A D | trace-events | 13 riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector) "Interrupt cause 0x%x sent via vecto…
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| /qemu/target/i386/whpx/ |
| A D | whpx-internal.h | 78 WHV_INTERRUPT_CONTROL* Interrupt, UINT32 InterruptControlSize)) \
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| /qemu/docs/system/devices/ |
| A D | ivshmem.rst | 19 shared memory region. Interrupt support requires using a shared memory
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| /qemu/docs/system/riscv/ |
| A D | shakti-c.rst | 23 * Platform-Level Interrupt Controller (PLIC)
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| A D | sifive_u.rst | 15 * Platform-Level Interrupt Controller (PLIC)
16 * Power, Reset, Clock, Interrupt (PRCI)
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| A D | microchip-icicle-kit.rst | 21 * Platform-Level Interrupt Controller (PLIC)
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| /qemu/docs/system/ppc/ |
| A D | ppce500.rst | 14 * Multicore Programmable Interrupt Controller (MPIC) with MSI support
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