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Searched refs:TO_REG (Results 1 – 12 of 12) sorted by relevance

/qemu/hw/misc/
A Daspeed_scu.c24 #define TO_REG(offset) ((offset) >> 2) macro
135 #define AST2600_CLK TO_REG(0x40)
311 int reg = TO_REG(offset); in aspeed_scu_read()
343 int reg = TO_REG(offset); in aspeed_ast2400_scu_write()
382 int reg = TO_REG(offset); in aspeed_ast2500_scu_write()
680 int reg = TO_REG(offset); in aspeed_ast2600_scu_read()
714 int reg = TO_REG(offset); in aspeed_ast2600_scu_write()
855 int reg = TO_REG(offset); in aspeed_ast2700_scu_read()
879 int reg = TO_REG(offset); in aspeed_ast2700_scu_write()
964 int reg = TO_REG(offset); in aspeed_ast2700_scuio_read()
[all …]
A Daspeed_lpc.c20 #define TO_REG(offset) ((offset) >> 2) macro
22 #define HICR0 TO_REG(0x00)
26 #define HICR1 TO_REG(0x04)
27 #define HICR2 TO_REG(0x08)
31 #define HICR3 TO_REG(0x0C)
32 #define HICR4 TO_REG(0x10)
34 #define IDR1 TO_REG(0x24)
35 #define IDR2 TO_REG(0x28)
36 #define IDR3 TO_REG(0x2C)
314 int reg = TO_REG(offset); in aspeed_lpc_read()
[all …]
A Daspeed_xdma.c48 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro
56 val = xdma->regs[TO_REG(addr)]; in aspeed_xdma_read()
75 xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()
77 idx = TO_REG(addr); in aspeed_xdma_write()
79 xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx]; in aspeed_xdma_write()
86 xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete; in aspeed_xdma_write()
88 if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) { in aspeed_xdma_write()
99 xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask; in aspeed_xdma_write()
103 idx = TO_REG(addr); in aspeed_xdma_write()
109 xdma->regs[TO_REG(addr)] = val32; in aspeed_xdma_write()
[all …]
A Daspeed_sli.c19 #define TO_REG(addr) ((addr) >> 2) macro
24 int reg = TO_REG(addr); in aspeed_sli_read()
41 int reg = TO_REG(addr); in aspeed_sli_write()
57 int reg = TO_REG(addr); in aspeed_sliio_read()
74 int reg = TO_REG(addr); in aspeed_sliio_write()
/qemu/hw/fsi/
A Daspeed_apb2opb.c18 #define TO_REG(x) (x >> 2) macro
20 #define APB2OPB_VERSION TO_REG(0x00)
21 #define APB2OPB_TRIGGER TO_REG(0x04)
23 #define APB2OPB_CONTROL TO_REG(0x08)
26 #define APB2OPB_OPB2FSI TO_REG(0x0c)
29 #define APB2OPB_OPB0_SEL TO_REG(0x10)
30 #define APB2OPB_OPB1_SEL TO_REG(0x28)
62 #define APB2OPB_OPB0_READ_DATA TO_REG(0x84)
63 #define APB2OPB_OPB1_READ_DATA TO_REG(0x90)
98 unsigned int reg = TO_REG(addr); in fsi_aspeed_apb2opb_read()
[all …]
A Dfsi-master.c17 #define TO_REG(x) ((x) >> 2) macro
19 #define FSI_MENP0 TO_REG(0x010)
20 #define FSI_MENP32 TO_REG(0x014)
21 #define FSI_MSENP0 TO_REG(0x018)
22 #define FSI_MLEVP0 TO_REG(0x018)
23 #define FSI_MSENP32 TO_REG(0x01c)
24 #define FSI_MLEVP32 TO_REG(0x01c)
25 #define FSI_MCENP0 TO_REG(0x020)
26 #define FSI_MREFP0 TO_REG(0x020)
40 int reg = TO_REG(addr); in fsi_master_read()
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A Dcfam.c32 #define TO_REG(x) ((x) >> 2) macro
34 #define CFAM_CONFIG_CHIP_ID TO_REG(0x00)
35 #define CFAM_CONFIG_PEEK_STATUS TO_REG(0x04)
70 switch (TO_REG(addr)) { in fsi_cfam_config_write()
A Dfsi.c14 #define TO_REG(x) ((x) >> 2) macro
25 int reg = TO_REG(addr); in fsi_slave_read()
43 int reg = TO_REG(addr); in fsi_slave_write()
A Dlbus.c15 #define TO_REG(offset) ((offset) >> 2) macro
41 int reg = TO_REG(addr); in fsi_scratchpad_read()
61 int reg = TO_REG(addr); in fsi_scratchpad_write()
/qemu/hw/adc/
A Daspeed_adc.c42 #define TO_REG(addr) (addr >> 2) macro
44 #define ENGINE_CONTROL TO_REG(0x00)
45 #define INTERRUPT_CONTROL TO_REG(0x04)
46 #define VGA_DETECT_CONTROL TO_REG(0x08)
47 #define CLOCK_CONTROL TO_REG(0x0C)
48 #define DATA_CHANNEL_1_AND_0 TO_REG(0x10)
49 #define DATA_CHANNEL_7_AND_6 TO_REG(0x1C)
50 #define DATA_CHANNEL_9_AND_8 TO_REG(0x20)
51 #define DATA_CHANNEL_15_AND_14 TO_REG(0x2C)
111 int reg = TO_REG(addr); in aspeed_adc_engine_read()
[all …]
/qemu/hw/sd/
A Daspeed_sdhci.c36 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro
64 val = sdhci->regs[TO_REG(addr)]; in aspeed_sdhci_read()
87 sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; in aspeed_sdhci_write()
113 sdhci->regs[TO_REG(addr)] = (uint32_t)val; in aspeed_sdhci_write()
135 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n); in aspeed_sdhci_set_irq()
139 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n); in aspeed_sdhci_set_irq()
188 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0; in aspeed_sdhci_reset()
190 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1; in aspeed_sdhci_reset()
192 sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET; in aspeed_sdhci_reset()
A Dcadence_sdhci.c49 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro
64 s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; in cadence_sdhci_reset()
74 val = s->regs[TO_REG(addr)]; in cadence_sdhci_read()
107 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
114 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
117 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()

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