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Searched refs:attrs (Results 1 – 25 of 115) sorted by relevance

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/qemu/hw/intc/
A Darm_gicv3_dist.c581 r = gicd_read_irouter(s, attrs, irq); in gicd_readl()
624 if (attrs.secure) { in gicd_writel()
801 r = gicd_read_irouter(s, attrs, irq); in gicd_writel()
803 gicd_write_irouter(s, attrs, irq, r); in gicd_writel()
859 r = gicd_readb(s, offset, data, attrs); in gicv3_dist_read()
862 r = gicd_readw(s, offset, data, attrs); in gicv3_dist_read()
865 r = gicd_readl(s, offset, data, attrs); in gicv3_dist_read()
868 r = gicd_readq(s, offset, data, attrs); in gicv3_dist_read()
900 r = gicd_writeb(s, offset, data, attrs); in gicv3_dist_write()
903 r = gicd_writew(s, offset, data, attrs); in gicv3_dist_write()
[all …]
A Darm_gic.c665 MemTxAttrs attrs) in gic_dist_set_priority() argument
667 if (s->security_extn && !attrs.secure) { in gic_dist_set_priority()
700 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_set_priority_mask()
716 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_get_priority_mask()
732 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_get_cpu_control()
748 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_set_cpu_control()
779 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_get_running_priority()
803 if (gic_cpu_ns_access(s, cpu, attrs)) { in gic_eoi_split()
826 if (!gic_eoi_split(s, cpu, attrs)) { in gic_deactivate_irq()
938 if (!gic_eoi_split(s, cpu, attrs)) { in gic_complete_irq()
[all …]
A Darm_gicv3_redist.c42 val &= mask_group(cs, attrs); in gicr_write_bitmap_reg()
51 val &= mask_group(cs, attrs); in gicr_write_set_bitmap_reg()
60 val &= mask_group(cs, attrs); in gicr_write_clear_bitmap_reg()
68 reg &= mask_group(cs, attrs); in gicr_read_bitmap_reg()
592 mask = mask_group(cs, attrs) & 0xffff0000U; in gicr_writel()
737 r = gicr_readb(cs, offset, data, attrs); in gicv3_redist_read()
740 r = gicr_readl(cs, offset, data, attrs); in gicv3_redist_read()
743 r = gicr_readll(cs, offset, data, attrs); in gicv3_redist_read()
796 r = gicr_writeb(cs, offset, data, attrs); in gicv3_redist_write()
799 r = gicr_writel(cs, offset, data, attrs); in gicv3_redist_write()
[all …]
A Dloongson_ipi_common.c61 if (attrs.requester_id >= ipi->num_cpu) { in loongson_ipi_iocsr_readl()
65 s = &ipi->cpu[attrs.requester_id]; in loongson_ipi_iocsr_readl()
117 attrs.requester_id = cs->cpu_index; in mail_send()
118 return send_ipi_data(ipi, cs, val, addr, attrs); in mail_send()
137 attrs.requester_id = cs->cpu_index; in any_send()
138 return send_ipi_data(ipi, cs, val, addr, attrs); in any_send()
186 BIT(vector), 4, attrs); in loongson_ipi_core_writel()
203 if (attrs.requester_id >= ipi->num_cpu) { in loongson_ipi_iocsr_writel()
207 s = &ipi->cpu[attrs.requester_id]; in loongson_ipi_iocsr_writel()
231 ret = mail_send(ipi, val, attrs); in loongson_ipi_writeq()
[all …]
A Darmv7m_nvic.c1015 if (!attrs.secure) { in nvic_readl()
1058 if (attrs.secure) { in nvic_readl()
1089 if (attrs.secure) { in nvic_readl()
1115 if (!attrs.secure) { in nvic_readl()
1126 if (attrs.secure) { in nvic_readl()
1507 if (attrs.secure) { in nvic_readl()
1691 if (attrs.secure) { in nvic_writel()
1715 if (attrs.secure) { in nvic_writel()
2219 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { in nvic_sysreg_read()
2350 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { in nvic_sysreg_write()
[all …]
/qemu/system/
A Dmemory_ldst.c.inc24 hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
36 mr = TRANSLATE(addr, &addr1, &l, false, attrs);
105 mr = TRANSLATE(addr, &addr1, &l, false, attrs);
172 mr = TRANSLATE(addr, &addr1, &l, false, attrs);
209 mr = TRANSLATE(addr, &addr1, &l, false, attrs);
279 mr = TRANSLATE(addr, &addr1, &l, true, attrs);
305 hwaddr addr, uint32_t val, MemTxAttrs attrs,
316 mr = TRANSLATE(addr, &addr1, &l, true, attrs);
379 mr = TRANSLATE(addr, &addr1, &l, true, attrs);
401 hwaddr addr, uint16_t val, MemTxAttrs attrs,
[all …]
A Dphysmem.c536 attrs); in address_space_get_iotlb_entry()
563 MemTxAttrs attrs) in flatview_translate() argument
2430 MemTxAttrs attrs) in subpage_accepts() argument
2509 int asidx = cpu_asidx_from_attrs(cpu, attrs); in iotlb_to_section()
2742 if (likely(!attrs.memory)) { in flatview_access_allowed()
2958 MemTxAttrs attrs, in address_space_write() argument
3185 MemTxAttrs attrs) in address_space_access_valid() argument
3232 MemTxAttrs attrs) in address_space_map() argument
3277 flatview_read(fv, addr, attrs, in address_space_map()
3563 MemTxAttrs attrs; in cpu_memory_rw_debug() local
[all …]
/qemu/docs/sphinx/
A Ddbusparser.py220 anno = Annotation(attrs["name"], attrs["value"])
227 if "name" in attrs and self.doc_comment_last_symbol == attrs["name"]:
250 prop = Property(attrs["name"], attrs["type"], attrs["access"])
255 anno = Annotation(attrs["name"], attrs["value"])
284 anno = Annotation(attrs["name"], attrs["value"])
292 if "name" in attrs and attrs["name"] in self.doc_comment_params:
312 anno = Annotation(attrs["name"], attrs["value"])
320 if "name" in attrs and attrs["name"] in self.doc_comment_params:
332 anno = Annotation(attrs["name"], attrs["value"])
341 anno = Annotation(attrs["name"], attrs["value"])
[all …]
/qemu/include/exec/
A Dmemory_ldst.h.inc24 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
26 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
28 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
30 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
39 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
41 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
43 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
45 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
47 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
49 hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
[all …]
A Dmemory_ldst_cached.h.inc28 hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
35 return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
40 hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
47 return ADDRESS_SPACE_LD_CACHED_SLOW(l)(cache, addr, attrs, result);
52 hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
75 hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
81 ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result);
86 hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
92 ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
97 hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
[all …]
A Dmemory.h281 MemTxAttrs attrs);
286 MemTxAttrs attrs);
307 MemTxAttrs attrs);
1889 MemTxAttrs attrs);
2575 MemTxAttrs attrs);
2591 MemTxAttrs attrs);
2654 MemTxAttrs attrs, void *buf,
2671 MemTxAttrs attrs,
2697 MemTxAttrs attrs,
2771 hwaddr addr, MemTxAttrs attrs, MemTxResult *result) in address_space_ldub_cached() argument
[all …]
/qemu/include/sysemu/
A Ddma.h78 attrs); in dma_memory_valid()
87 return address_space_rw(as, addr, attrs, in dma_memory_rw_relaxed()
148 MemTxAttrs attrs) in dma_memory_read() argument
151 DMA_DIRECTION_TO_DEVICE, attrs); in dma_memory_read()
169 MemTxAttrs attrs) in dma_memory_write() argument
172 DMA_DIRECTION_FROM_DEVICE, attrs); in dma_memory_write()
213 attrs); in dma_memory_map()
261 return dma_memory_read(as, addr, val, 1, attrs); in ldub_dma()
267 return dma_memory_write(as, addr, &val, 1, attrs); in stb_dma()
304 QEMUSGList *sg, MemTxAttrs attrs);
[all …]
/qemu/hw/misc/
A Dtz-msc.c139 attrs.secure = 1; in tz_msc_read()
140 attrs.unspecified = 0; in tz_msc_read()
143 attrs.secure = 0; in tz_msc_read()
144 attrs.unspecified = 0; in tz_msc_read()
150 data = address_space_ldub(as, addr, attrs, &res); in tz_msc_read()
181 attrs.secure = 1; in tz_msc_write()
182 attrs.unspecified = 0; in tz_msc_write()
185 attrs.secure = 0; in tz_msc_write()
186 attrs.unspecified = 0; in tz_msc_write()
192 address_space_stb(as, addr, val, attrs, &res); in tz_msc_write()
[all …]
A Dtz-ppc.c80 static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) in tz_ppc_check() argument
93 (attrs.user && !s->cfg_ap[n])) { in tz_ppc_check()
115 if (!tz_ppc_check(s, n, attrs)) { in tz_ppc_read()
116 trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); in tz_ppc_read()
127 data = address_space_ldub(as, addr, attrs, &res); in tz_ppc_read()
154 if (!tz_ppc_check(s, n, attrs)) { in tz_ppc_write()
155 trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); in tz_ppc_write()
165 address_space_stb(as, addr, val, attrs, &res); in tz_ppc_write()
168 address_space_stw_le(as, addr, val, attrs, &res); in tz_ppc_write()
171 address_space_stl_le(as, addr, val, attrs, &res); in tz_ppc_write()
[all …]
A Dtz-mpc.c141 unsigned size, MemTxAttrs attrs) in tz_mpc_reg_read() argument
147 if (!attrs.secure && offset < A_PIDR4) { in tz_mpc_reg_read()
233 unsigned size, MemTxAttrs attrs) in tz_mpc_reg_write() argument
240 if (!attrs.secure && offset < A_PIDR4) { in tz_mpc_reg_write()
375 attrs.requester_id & 0xffff); in tz_mpc_handle_block()
377 ~attrs.secure); in tz_mpc_handle_block()
398 trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure); in tz_mpc_mem_blocked_read()
401 return tz_mpc_handle_block(s, addr, attrs); in tz_mpc_mem_blocked_read()
410 trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure); in tz_mpc_mem_blocked_write()
412 return tz_mpc_handle_block(s, addr, attrs); in tz_mpc_mem_blocked_write()
[all …]
A Darmv7m_ras.c17 MemTxAttrs attrs) in ras_read() argument
19 if (attrs.user) { in ras_read()
43 MemTxAttrs attrs) in ras_write() argument
45 if (attrs.user) { in ras_write()
/qemu/target/i386/
A Dhelper.c249 *attrs = cpu_get_mem_attrs(env); in x86_cpu_get_phys_page_attrs_debug()
638 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_ldub_phys() local
648 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_lduw_phys() local
658 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_ldl_phys() local
668 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_ldq_phys() local
678 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_stb_phys() local
681 address_space_stb(as, addr, val, attrs, NULL); in x86_stb_phys()
688 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_stl_phys_notdirty() local
698 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_stw_phys() local
708 MemTxAttrs attrs = cpu_get_mem_attrs(env); in x86_stl_phys() local
[all …]
/qemu/hw/arm/
A Darmv7m.c139 if (attrs.secure) { in v7m_sysreg_ns_write()
141 attrs.secure = 0; in v7m_sysreg_ns_write()
146 if (attrs.user) { in v7m_sysreg_ns_write()
159 if (attrs.secure) { in v7m_sysreg_ns_read()
161 attrs.secure = 0; in v7m_sysreg_ns_read()
166 if (attrs.user) { in v7m_sysreg_ns_read()
195 MemTxAttrs attrs) in v7m_systick_read() argument
203 attrs); in v7m_systick_read()
218 MemTxAttrs attrs) in ppb_default_read() argument
222 if (attrs.user) { in ppb_default_read()
[all …]
/qemu/target/arm/
A Dptw.c309 MemTxAttrs attrs = { in granule_protection_check() local
670 MemTxAttrs attrs = { in arm_ldl_ptw() local
1696 uint64_t attrs; in get_phys_addr_lpae() local
2026 result->cacheattrs.attrs = extract32(attrs, 2, 4); in get_phys_addr_lpae()
3125 switch (s2.attrs) { in combined_attrs_fwb()
3128 return s1.attrs; in combined_attrs_fwb()
3179 s1.attrs = 0xff; in combine_cacheattrs()
3209 if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) { in combine_cacheattrs()
3215 ret.attrs = 0xf0; in combine_cacheattrs()
3410 result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure); in get_phys_addr_twostage()
[all …]
/qemu/ui/
A Degl-helpers.c309 EGLint attrs[64]; in egl_dmabuf_import_texture() local
318 attrs[i++] = EGL_WIDTH; in egl_dmabuf_import_texture()
320 attrs[i++] = EGL_HEIGHT; in egl_dmabuf_import_texture()
322 attrs[i++] = EGL_LINUX_DRM_FOURCC_EXT; in egl_dmabuf_import_texture()
325 attrs[i++] = EGL_DMA_BUF_PLANE0_FD_EXT; in egl_dmabuf_import_texture()
326 attrs[i++] = qemu_dmabuf_get_fd(dmabuf); in egl_dmabuf_import_texture()
327 attrs[i++] = EGL_DMA_BUF_PLANE0_PITCH_EXT; in egl_dmabuf_import_texture()
329 attrs[i++] = EGL_DMA_BUF_PLANE0_OFFSET_EXT; in egl_dmabuf_import_texture()
330 attrs[i++] = 0; in egl_dmabuf_import_texture()
340 attrs[i++] = EGL_NONE; in egl_dmabuf_import_texture()
[all …]
/qemu/hw/core/
A Dcpu-sysemu.c51 MemTxAttrs *attrs) in cpu_get_phys_page_attrs_debug() argument
56 return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); in cpu_get_phys_page_attrs_debug()
59 *attrs = MEMTXATTRS_UNSPECIFIED; in cpu_get_phys_page_attrs_debug()
65 MemTxAttrs attrs = {}; in cpu_get_phys_page_debug() local
67 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); in cpu_get_phys_page_debug()
70 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) in cpu_asidx_from_attrs() argument
75 ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs); in cpu_asidx_from_attrs()
/qemu/target/microblaze/
A Dhelper.c48 MemTxAttrs attrs = {}; in mb_cpu_tlb_fill() local
50 attrs.secure = mb_cpu_access_is_secure(cpu, access_type); in mb_cpu_tlb_fill()
56 tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, in mb_cpu_tlb_fill()
68 tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, in mb_cpu_tlb_fill()
229 MemTxAttrs *attrs) in mb_cpu_get_phys_page_attrs_debug() argument
238 *attrs = (MemTxAttrs) {}; in mb_cpu_get_phys_page_attrs_debug()
239 attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); in mb_cpu_get_phys_page_attrs_debug()
/qemu/hw/net/
A Dtulip.c73 const MemTxAttrs attrs = { .memory = true }; in tulip_desc_read() local
76 ldl_be_pci_dma(&s->dev, p, &desc->status, attrs); in tulip_desc_read()
77 ldl_be_pci_dma(&s->dev, p + 4, &desc->control, attrs); in tulip_desc_read()
81 ldl_le_pci_dma(&s->dev, p, &desc->status, attrs); in tulip_desc_read()
82 ldl_le_pci_dma(&s->dev, p + 4, &desc->control, attrs); in tulip_desc_read()
91 const MemTxAttrs attrs = { .memory = true }; in tulip_desc_write() local
94 stl_be_pci_dma(&s->dev, p, desc->status, attrs); in tulip_desc_write()
95 stl_be_pci_dma(&s->dev, p + 4, desc->control, attrs); in tulip_desc_write()
96 stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); in tulip_desc_write()
99 stl_le_pci_dma(&s->dev, p, desc->status, attrs); in tulip_desc_write()
[all …]
/qemu/hw/pci-host/
A Ddino.c59 MemTxAttrs attrs) in dino_chip_mem_valid() argument
95 MemTxAttrs attrs) in dino_chip_read_with_attrs() argument
111 val = address_space_ldub(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
114 val = address_space_lduw_be(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
117 val = address_space_ldl_be(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
188 MemTxAttrs attrs) in dino_chip_write_with_attrs() argument
206 address_space_stb(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
209 address_space_stw_be(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
212 address_space_stl_be(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
/qemu/include/hw/pci/
A Dpci_device.h245 DMADirection dir, MemTxAttrs attrs) in pci_dma_rw() argument
248 dir, attrs); in pci_dma_rw()
293 MemTxAttrs attrs) \
295 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
300 MemTxAttrs attrs) \
302 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \

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