| /qemu/tests/qtest/ |
| A D | qtest_aspeed.c | 18 static void aspeed_i2c_startup(QTestState *s, uint32_t baseaddr, in aspeed_i2c_startup() argument
26 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0); in aspeed_i2c_startup()
28 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v); in aspeed_i2c_startup()
34 qtest_writel(s, baseaddr + A_I2CD_CMD, in aspeed_i2c_startup()
38 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg); in aspeed_i2c_startup()
39 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD); in aspeed_i2c_startup()
50 aspeed_i2c_startup(s, baseaddr, slave_addr, reg); in aspeed_i2c_read_n()
54 v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8; in aspeed_i2c_read_n()
58 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD); in aspeed_i2c_read_n()
87 aspeed_i2c_startup(s, baseaddr, slave_addr, reg); in aspeed_i2c_write_n()
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| A D | qtest_aspeed.h | 27 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
29 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
31 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg);
32 void aspeed_i2c_writeb(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
34 void aspeed_i2c_writew(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
36 void aspeed_i2c_writel(QTestState *s, uint32_t baseaddr, uint8_t slave_addr,
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| /qemu/hw/arm/ |
| A D | smmu-common.c | 317 dma_addr_t addr = baseaddr + index * sizeof(*pte); in get_pte()
327 trace_smmu_get_pte(baseaddr, index, addr, *pte); in get_pte()
440 dma_addr_t baseaddr, indexmask; in smmu_ptw_64_s1() local
456 baseaddr = extract64(tt->ttb, 0, cfg->oas); in smmu_ptw_64_s1()
457 baseaddr &= ~indexmask; in smmu_ptw_64_s1()
467 if (get_pte(baseaddr, offset, &pte, info)) { in smmu_ptw_64_s1()
471 baseaddr, offset, pte); in smmu_ptw_64_s1()
503 trace_smmu_ptw_block_pte(stage, level, baseaddr, in smmu_ptw_64_s1()
584 baseaddr &= ~indexmask; in smmu_ptw_64_s2()
603 if (get_pte(baseaddr, offset, &pte, info)) { in smmu_ptw_64_s2()
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| A D | trace-events | 8 …t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx…
9 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, ui…
10 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64…
11 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_…
12 smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" in…
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| A D | mps3r.c | 331 hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq, in create_uart() argument
345 memory_region_add_subregion(mem, baseaddr, in create_uart()
446 hwaddr baseaddr = 0xe0205000 + i * 0x1000; in mps3r_common_init() local
449 create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr, in mps3r_common_init()
506 hwaddr baseaddr = 0xe0104000 + i * 0x1000; in mps3r_common_init() local
510 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr); in mps3r_common_init()
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| /qemu/hw/smbios/ |
| A D | smbios_type_38.c | 30 uint64_t baseaddr = info->base_address; in smbios_build_one_type_38() local
45 baseaddr |= 1; in smbios_build_one_type_38()
51 baseaddr <<= 1; in smbios_build_one_type_38()
55 t->base_address = cpu_to_le64(baseaddr); in smbios_build_one_type_38()
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| /qemu/hw/mem/ |
| A D | sparse-mem.c | 29 uint64_t baseaddr; member
101 DEFINE_PROP_UINT64("baseaddr", SparseMemState, baseaddr, 0x0),
132 assert(s->baseaddr + s->length > s->baseaddr); in sparse_mem_realize()
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| /qemu/hw/sparc64/ |
| A D | sun4u_iommu.c | 80 hwaddr baseaddr, offset; in sun4u_translate_iommu() local
101 baseaddr = is->regs[IOMMU_BASE >> 3]; in sun4u_translate_iommu()
159 tte = address_space_ldq_be(&address_space_memory, baseaddr + offset, in sun4u_translate_iommu()
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| /qemu/pc-bios/ |
| A D | petalogix-s3adsp1800.dts | 34 d-cache-baseaddr = <0x90000000>;
39 i-cache-baseaddr = <0x90000000>;
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| A D | petalogix-ml605.dts | 39 d-cache-baseaddr = < 0x50000000 >;
44 i-cache-baseaddr = < 0x50000000 >;
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| /qemu/disas/ |
| A D | mips.c | 5544 bfd_vma baseaddr;
5549 baseaddr = memaddr + 2;
5552 baseaddr = memaddr - 2;
5558 baseaddr = memaddr;
5574 baseaddr = memaddr - 4;
5584 baseaddr = memaddr - 2;
5587 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
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