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Searched refs:cc (Results 1 – 25 of 216) sorted by relevance

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/qemu/hw/core/
A Dcpu-sysemu.c28 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_paging_enabled() local
30 if (cc->sysemu_ops->get_paging_enabled) { in cpu_paging_enabled()
40 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_memory_mapping() local
53 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_phys_page_attrs_debug() local
84 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf32_qemunote() local
95 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf32_note() local
106 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf64_qemunote() local
117 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf64_note() local
127 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_virtio_is_big_endian() local
137 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_crash_info() local
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/qemu/tests/tcg/s390x/
A Dadd-logical-with-carry.c42 unsigned long c, int *cc) in test32rm() argument
50 : [a] "+&r" (a32), [cc] "+&r" (*cc) in test32rm()
53 *cc >>= 28; in test32rm()
68 : [a] "+&r" (a32), [c] "+&r" (c32), [cc] "+&r" (*cc) in test32mr()
71 *cc >>= 28; in test32mr()
84 : [a] "+&r" (a), [cc] "+&r" (*cc) in test64rm()
87 *cc >>= 28; in test64rm()
99 : [a] "+&r" (a), [c] "+&r" (c), [cc] "+&r" (*cc) in test64mr()
102 *cc >>= 28; in test64mr()
132 int cc; in main() local
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A Drxsbg.c10 rxsbg(unsigned long *r1, unsigned long r2, int i3, int i4, int i5, int *cc) in rxsbg() argument
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in rxsbg()
17 *cc = (*cc >> 28) & 3; in rxsbg()
23 int cc; in test_cc0() local
25 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc0()
27 assert(cc == 0); in test_cc0()
33 int cc; in test_cc1() local
35 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc1()
37 assert(cc == 1); in test_cc1()
A Dchrl.c7 uint32_t program_mask, cc; in test_chrl() local
21 cc = program_mask >> 28; in test_chrl()
22 assert(!cc); in test_chrl()
36 cc = program_mask >> 28; in test_chrl()
37 assert(!cc); in test_chrl()
42 uint32_t program_mask, cc; in test_cghrl() local
56 cc = program_mask >> 28; in test_cghrl()
57 assert(!cc); in test_cghrl()
71 cc = program_mask >> 28; in test_cghrl()
72 assert(!cc); in test_cghrl()
A Dlcbb.c10 lcbb(long *r1, void *dxb2, int m3, int *cc) in lcbb() argument
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in lcbb()
17 *cc = (*cc >> 28) & 3; in lcbb()
26 int cc; in test_lcbb() local
28 lcbb(&r1, p, m3, &cc); in test_lcbb()
30 assert(cc == exp_cc); in test_lcbb()
A Dclst.c9 int cc; in clst() local
17 : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=r" (cc) in clst()
22 } while (cc == 3); in clst()
24 return cc; in clst()
66 int cc; in main() local
72 cc = clst(t->sep, &s1, &s2); in main()
73 if (cc != t->exp_cc || in main()
A Dcdsg.c27 int cc; in cdsg() local
38 , [cc] "=r" (cc) in cdsg()
45 return (cc >> 28) & 3; in cdsg()
51 int cc; in cdsg_loop() local
63 cc = cdsg(&orig0, &orig1, new0, new1, &val); in cdsg_loop()
65 if (cc == 0) { in cdsg_loop()
70 assert(cc == 1); in cdsg_loop()
A Dcsst.c15 uint64_t cc; in main() local
25 [cc] "=r" (cc) in main()
29 cc = (cc >> 28) & 3; in main()
30 if (cc) { in main()
A Dexrl-trt.c10 uint64_t cc; in main() local
27 [cc] "=r" (cc) in main()
32 cc = (cc >> 28) & 3; in main()
33 if (cc != 2) { in main()
A Dexrl-trtr.c10 uint64_t cc; in main() local
27 [cc] "=r" (cc) in main()
32 cc = (cc >> 28) & 3; in main()
33 if (cc != 1) { in main()
A Dclgebr.c14 int cc; in main() local
20 , [cc] "=r" (cc) in main()
25 cc >>= 28; in main()
28 assert(cc == 3); in main()
A Dcgebra.c14 int cc; in main() local
20 , [cc] "=r" (cc) in main()
25 cc >>= 28; in main()
28 assert(cc == 3); in main()
/qemu/backends/
A Dcryptodev-vhost.c61 crypto->cc = options->cc; in cryptodev_vhost_init()
124 if (!cc) { in cryptodev_get_vhost()
128 switch (cc->type) { in cryptodev_get_vhost()
157 cc->vring_enable = enable; in vhost_set_vring_enable()
181 CryptoDevBackendClient *cc; in cryptodev_vhost_start() local
189 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_start()
219 if (cc->vring_enable) { in cryptodev_vhost_start()
221 r = vhost_set_vring_enable(cc, b, i, cc->vring_enable); in cryptodev_vhost_start()
253 CryptoDevBackendClient *cc; in cryptodev_vhost_stop() local
278 CryptoDevBackendClient *cc; in cryptodev_vhost_virtqueue_mask() local
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A Dcryptodev-vhost-user.c107 options.cc = b->conf.peers.ccs[i]; in cryptodev_vhost_user_start()
188 CryptoDevBackendClient *cc; in cryptodev_vhost_user_init() local
201 cc = cryptodev_backend_new_client(); in cryptodev_vhost_user_init()
204 cc->queue_index = i; in cryptodev_vhost_user_init()
207 backend->conf.peers.ccs[i] = cc; in cryptodev_vhost_user_init()
240 CryptoDevBackendClient *cc = in cryptodev_vhost_user_crypto_create_session() local
311 CryptoDevBackendClient *cc = in cryptodev_vhost_user_close_session() local
343 CryptoDevBackendClient *cc; in cryptodev_vhost_user_cleanup() local
348 cc = backend->conf.peers.ccs[i]; in cryptodev_vhost_user_cleanup()
349 if (cc) { in cryptodev_vhost_user_cleanup()
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/qemu/accel/
A Daccel-target.c62 CPUClass *cc = CPU_CLASS(klass); in accel_init_cpu_int_aux() local
75 cc->accel_cpu = accel_cpu; in accel_init_cpu_int_aux()
77 accel_cpu->cpu_class_init(cc); in accel_init_cpu_int_aux()
79 if (cc->init_accel_cpu) { in accel_init_cpu_int_aux()
80 cc->init_accel_cpu(accel_cpu, cc); in accel_init_cpu_int_aux()
115 CPUClass *cc = CPU_GET_CLASS(cpu); in accel_cpu_instance_init() local
117 if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) { in accel_cpu_instance_init()
118 cc->accel_cpu->cpu_instance_init(cpu); in accel_cpu_instance_init()
124 CPUClass *cc = CPU_GET_CLASS(cpu); in accel_cpu_common_realize() local
129 if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize in accel_cpu_common_realize()
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/qemu/pc-bios/optionrom/
A DMakefile24 cc-test = $(CC) -Werror $1 -c -o /dev/null -xc /dev/null >/dev/null 2>/dev/null
25 cc-option = if $(call cc-test, $1); then \
31 config-cc.mak: Makefile
32 $(quiet-@)($(call cc-option,-fcf-protection=none); \
33 $(call cc-option,-fno-pie); \
34 $(call cc-option,-no-pie); \
35 $(call cc-option,-fno-stack-protector); \
36 $(call cc-option,-Wno-array-bounds)) 3> config-cc.mak
37 -include config-cc.mak
64 rm -f config-cc.mak
/qemu/target/tricore/
A Dcpu.c184 CPUClass *cc = CPU_CLASS(c); in tricore_cpu_class_init() local
193 cc->class_by_name = tricore_cpu_class_by_name; in tricore_cpu_class_init()
194 cc->has_work = tricore_cpu_has_work; in tricore_cpu_class_init()
195 cc->mmu_index = tricore_cpu_mmu_index; in tricore_cpu_class_init()
199 cc->gdb_num_core_regs = 44; in tricore_cpu_class_init()
200 cc->gdb_arch_name = tricore_gdb_arch_name; in tricore_cpu_class_init()
202 cc->dump_state = tricore_cpu_dump_state; in tricore_cpu_class_init()
203 cc->set_pc = tricore_cpu_set_pc; in tricore_cpu_class_init()
204 cc->get_pc = tricore_cpu_get_pc; in tricore_cpu_class_init()
205 cc->sysemu_ops = &tricore_sysemu_ops; in tricore_cpu_class_init()
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/qemu/target/s390x/
A Dcpu.c107 assert(cc <= 3); in s390_cpu_get_psw_mask()
109 r |= cc << 44; in s390_cpu_get_psw_mask()
380 CPUClass *cc = CPU_CLASS(scc); in s390_cpu_class_init() local
393 cc->has_work = s390_cpu_has_work; in s390_cpu_class_init()
394 cc->mmu_index = s390x_cpu_mmu_index; in s390_cpu_class_init()
395 cc->dump_state = s390_cpu_dump_state; in s390_cpu_class_init()
397 cc->set_pc = s390_cpu_set_pc; in s390_cpu_class_init()
398 cc->get_pc = s390_cpu_get_pc; in s390_cpu_class_init()
402 s390_cpu_class_init_sysemu(cc); in s390_cpu_class_init()
406 cc->gdb_arch_name = s390_gdb_arch_name; in s390_cpu_class_init()
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A Dsigp.c27 int cc; member
35 si->cc = SIGP_CC_STATUS_STORED; in set_sigp_status()
91 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_emergency()
105 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_start()
126 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_stop()
151 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_stop_and_store_status()
172 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_store_status_at_address()
225 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_store_adtl_status()
249 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_restart()
259 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_initial_cpu_reset()
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/qemu/target/rx/
A Dcpu.c210 CPUClass *cc = CPU_CLASS(klass); in rx_cpu_class_init() local
219 cc->class_by_name = rx_cpu_class_by_name; in rx_cpu_class_init()
220 cc->has_work = rx_cpu_has_work; in rx_cpu_class_init()
221 cc->mmu_index = riscv_cpu_mmu_index; in rx_cpu_class_init()
222 cc->dump_state = rx_cpu_dump_state; in rx_cpu_class_init()
223 cc->set_pc = rx_cpu_set_pc; in rx_cpu_class_init()
224 cc->get_pc = rx_cpu_get_pc; in rx_cpu_class_init()
227 cc->sysemu_ops = &rx_sysemu_ops; in rx_cpu_class_init()
231 cc->disas_set_info = rx_cpu_disas_set_info; in rx_cpu_class_init()
233 cc->gdb_core_xml_file = "rx-core.xml"; in rx_cpu_class_init()
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/qemu/target/xtensa/
A Dcpu.c248 CPUClass *cc = CPU_CLASS(oc); in xtensa_cpu_class_init() local
249 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); in xtensa_cpu_class_init()
258 cc->class_by_name = xtensa_cpu_class_by_name; in xtensa_cpu_class_init()
259 cc->has_work = xtensa_cpu_has_work; in xtensa_cpu_class_init()
260 cc->mmu_index = xtensa_cpu_mmu_index; in xtensa_cpu_class_init()
261 cc->dump_state = xtensa_cpu_dump_state; in xtensa_cpu_class_init()
262 cc->set_pc = xtensa_cpu_set_pc; in xtensa_cpu_class_init()
263 cc->get_pc = xtensa_cpu_get_pc; in xtensa_cpu_class_init()
266 cc->gdb_stop_before_watchpoint = true; in xtensa_cpu_class_init()
268 cc->sysemu_ops = &xtensa_sysemu_ops; in xtensa_cpu_class_init()
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/qemu/target/alpha/
A Dcpu.c243 CPUClass *cc = CPU_CLASS(oc); in alpha_cpu_class_init() local
249 cc->class_by_name = alpha_cpu_class_by_name; in alpha_cpu_class_init()
250 cc->has_work = alpha_cpu_has_work; in alpha_cpu_class_init()
251 cc->mmu_index = alpha_cpu_mmu_index; in alpha_cpu_class_init()
252 cc->dump_state = alpha_cpu_dump_state; in alpha_cpu_class_init()
253 cc->set_pc = alpha_cpu_set_pc; in alpha_cpu_class_init()
254 cc->get_pc = alpha_cpu_get_pc; in alpha_cpu_class_init()
259 cc->sysemu_ops = &alpha_sysemu_ops; in alpha_cpu_class_init()
261 cc->disas_set_info = alpha_cpu_disas_set_info; in alpha_cpu_class_init()
263 cc->tcg_ops = &alpha_tcg_ops; in alpha_cpu_class_init()
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/qemu/target/hppa/
A Dcpu.c241 CPUClass *cc = CPU_CLASS(oc); in hppa_cpu_class_init() local
247 cc->class_by_name = hppa_cpu_class_by_name; in hppa_cpu_class_init()
248 cc->has_work = hppa_cpu_has_work; in hppa_cpu_class_init()
249 cc->mmu_index = hppa_cpu_mmu_index; in hppa_cpu_class_init()
250 cc->dump_state = hppa_cpu_dump_state; in hppa_cpu_class_init()
251 cc->set_pc = hppa_cpu_set_pc; in hppa_cpu_class_init()
252 cc->get_pc = hppa_cpu_get_pc; in hppa_cpu_class_init()
257 cc->sysemu_ops = &hppa_sysemu_ops; in hppa_cpu_class_init()
259 cc->disas_set_info = hppa_cpu_disas_set_info; in hppa_cpu_class_init()
260 cc->gdb_num_core_regs = 128; in hppa_cpu_class_init()
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/qemu/tests/tcg/aarch64/
A DMakefile.target21 config-cc.mak: Makefile
23 fnia=`$(call cc-test,-fno-integrated-as) && echo -fno-integrated-as`; \
24 $(call cc-option,-march=armv8.1-a+sve, CROSS_CC_HAS_SVE); \
25 $(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
26 $(call cc-option,-march=armv8.2-a, CROSS_CC_HAS_ARMV8_2); \
27 $(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
28 $(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \
29 $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
30 $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
31 … $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme $$fnia, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
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/qemu/target/openrisc/
A Dcpu.c250 CPUClass *cc = CPU_CLASS(occ); in openrisc_cpu_class_init() local
259 cc->class_by_name = openrisc_cpu_class_by_name; in openrisc_cpu_class_init()
260 cc->has_work = openrisc_cpu_has_work; in openrisc_cpu_class_init()
261 cc->mmu_index = openrisc_cpu_mmu_index; in openrisc_cpu_class_init()
262 cc->dump_state = openrisc_cpu_dump_state; in openrisc_cpu_class_init()
263 cc->set_pc = openrisc_cpu_set_pc; in openrisc_cpu_class_init()
264 cc->get_pc = openrisc_cpu_get_pc; in openrisc_cpu_class_init()
269 cc->sysemu_ops = &openrisc_sysemu_ops; in openrisc_cpu_class_init()
271 cc->gdb_num_core_regs = 32 + 3; in openrisc_cpu_class_init()
272 cc->disas_set_info = openrisc_disas_set_info; in openrisc_cpu_class_init()
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