Searched refs:cleared (Results 1 – 25 of 27) sorted by relevance
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| /qemu/hw/misc/ |
| A D | stm32l4x5_exti.c | 217 const uint32_t cleared = s->pr[bank] & val64 & configurable_mask(bank); in stm32l4x5_exti_write() local
219 s->pr[bank] &= ~cleared; in stm32l4x5_exti_write()
221 s->swier[bank] &= ~cleared; in stm32l4x5_exti_write()
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| /qemu/block/ |
| A D | qcow2-cluster.c | 2002 int64_t cleared; in qcow2_cluster_discard() local
2018 if (cleared < 0) { in qcow2_cluster_discard()
2019 ret = cleared; in qcow2_cluster_discard()
2023 nb_clusters -= cleared; in qcow2_cluster_discard()
2024 offset += (cleared * s->cluster_size); in qcow2_cluster_discard()
2164 int64_t cleared; in qcow2_subcluster_zeroize() local
2215 cleared = zero_in_l2_slice(bs, offset, nb_clusters, flags); in qcow2_subcluster_zeroize()
2216 if (cleared < 0) { in qcow2_subcluster_zeroize()
2217 ret = cleared; in qcow2_subcluster_zeroize()
2221 nb_clusters -= cleared; in qcow2_subcluster_zeroize()
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| /qemu/tests/tcg/s390x/ |
| A D | Makefile.softmmu-target | 54 --bss-cleared $@.out
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| /qemu/docs/specs/ |
| A D | edu.rst | 55 below) is cleared.
74 Clear an interrupt. The value will be cleared from the interrupt
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| A D | acpi_mem_hotplug.rst | 64 Due to BUG in versions prior 2.4 that field isn't cleared
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| A D | rapl-msr.rst | 36 energy consumed since the last time the register was cleared. If you multiply
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| A D | acpi_cpu_hotplug.rst | 135 when bit #4 is set. In case bit #4 were set, it's cleared as
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| A D | fw_cfg.rst | 237 All bits cleared
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| /qemu/hw/timer/ |
| A D | hpet.c | 498 uint64_t old_val, new_val, cleared; in hpet_ram_write() local
609 cleared = new_val & s->isr; in hpet_ram_write()
611 if (cleared & (1 << i)) { in hpet_ram_write()
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| /qemu/docs/spin/ |
| A D | aio_notify_bug.promela | 3 * cleared too late, a wakeup could be lost.
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| /qemu/hw/misc/macio/ |
| A D | trace-events | 36 pmu_debug_protocol_clear_treq(int state) "TREQ cleared, clearing TACK, state: %d"
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| /qemu/hw/gpio/ |
| A D | aspeed_gpio.c | 815 uint32_t cleared; in aspeed_gpio_write() local
889 cleared = ctpop32(data & set->int_status); in aspeed_gpio_write()
890 if (s->pending && cleared) { in aspeed_gpio_write()
891 assert(s->pending >= cleared); in aspeed_gpio_write()
892 s->pending -= cleared; in aspeed_gpio_write()
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| /qemu/target/ppc/ |
| A D | power8-pmu-regs.c.inc | 68 /* 'ret' starts with all mask bits cleared */
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| /qemu/hw/nvme/ |
| A D | trace-events | 103 pci_nvme_mmio_stopped(void) "cleared controller enable bit"
105 pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
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| /qemu/hw/char/ |
| A D | trace-events | 93 exynos_uart_intclr(uint32_t channel, uint32_t reg) "UART%d: interrupts cleared: 0x%08"PRIx32
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| /qemu/docs/interop/ |
| A D | parallels.rst | 67 cleared in this case.
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| A D | qed_spec.txt | 138 …etes with no other errors besides leaks, the QED_F_NEED_CHECK bit can be cleared and the image can…
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| A D | bitmaps.rst | 274 Clears all dirty bits from a bitmap. ``+busy`` bitmaps cannot be cleared.
377 - The destination is not cleared prior to merge, so subsequent merge
784 ``+busy``. If the operation is successful, ``bitmap0`` will be cleared to
1205 cleared. It will contain all of the dirty bits it did at the start of the
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| /qemu/docs/ |
| A D | qcow2-cache.txt | 134 this difference stems from the fact that on Linux the cache can be cleared
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| /qemu/target/ppc/translate/ |
| A D | fixedpoint-impl.c.inc | 216 * that "the L field must be cleared, otherwise the instruction form is
254 * that "the L field must be cleared, otherwise the instruction form is
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| A D | fp-impl.c.inc | 480 /* Only the exception bits (including FX) should be cleared if read */
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| /qemu/docs/devel/migration/ |
| A D | postcopy.rst | 195 dirty anything any more. Instead, dirty bits are cleared when the relevant
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| /qemu/docs/devel/ |
| A D | multi-thread-tcg.rst | 126 book-keeping structures that need to be safely cleared.
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| /qemu/tcg/i386/ |
| A D | tcg-target.c.inc | 1705 bool cleared;
1796 cleared = false;
1799 cleared = true;
1805 if (!cleared) {
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| /qemu/target/i386/tcg/ |
| A D | emit.c.inc | 1545 * cleared) we need to store the inverse into C.
2586 * seem to work, but it does not on big-endian platforms; the cleared parts
2588 * byte order so that the cleared parts need to be at *lower* addresses.
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