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Searched refs:clk (Results 1 – 25 of 48) sorted by relevance

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/qemu/hw/core/
A Dclock.c26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
41 return clk; in clock_new()
47 clk->callback = cb; in clock_set_callback()
62 trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), in clock_set()
75 return muldiv64(clk->period, clk->multiplier, clk->divider); in clock_get_child_period()
84 if (clk->callback && (clk->callback_events & event)) { in clock_call_callback()
85 clk->callback(clk->callback_opaque, event); in clock_call_callback()
151 if (clk->multiplier == multiplier && clk->divider == divider) { in clock_set_mul_div()
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A Dclock-vmstate.c19 Clock *clk = opaque; in muldiv_needed() local
21 return clk->multiplier != 1 || clk->divider != 1; in muldiv_needed()
26 Clock *clk = opaque; in clock_pre_load() local
33 clk->multiplier = 1; in clock_pre_load()
34 clk->divider = 1; in clock_pre_load()
A Dqdev-clock.c25 bool output, Clock *clk) in qdev_init_clocklist() argument
42 ncl->alias = (clk != NULL); in qdev_init_clocklist()
48 if (clk == NULL) { in qdev_init_clocklist()
49 clk = CLOCK(object_new(TYPE_CLOCK)); in qdev_init_clocklist()
50 object_property_add_child(OBJECT(dev), name, OBJECT(clk)); in qdev_init_clocklist()
57 object_unref(OBJECT(clk)); in qdev_init_clocklist()
61 object_get_typename(OBJECT(clk)), in qdev_init_clocklist()
71 object_ref(OBJECT(clk)); in qdev_init_clocklist()
74 ncl->clock = clk; in qdev_init_clocklist()
A Dtrace-events26 clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
27 clock_disconnect(const char *clk) "'%s'"
28 clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
29 clock_propagate(const char *clk) "'%s'"
30 clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"H…
31 clock_set_mul_div(const char *clk, uint32_t oldmul, uint32_t mul, uint32_t olddiv, uint32_t div) "'…
/qemu/hw/misc/
A Domap_clk.c27 struct clk { struct
30 struct clk *parent; argument
582 void omap_clk_adduser(struct clk *clk, qemu_irq user) in omap_clk_adduser() argument
600 void omap_clk_get(struct clk *clk) in omap_clk_get() argument
605 void omap_clk_put(struct clk *clk) in omap_clk_put() argument
611 static void omap_clk_update(struct clk *clk) in omap_clk_update() argument
648 static void omap_clk_rate_update(struct clk *clk) in omap_clk_rate_update() argument
661 void omap_clk_reparent(struct clk *clk, struct clk *parent) in omap_clk_reparent() argument
680 void omap_clk_onoff(struct clk *clk, int on) in omap_clk_onoff() argument
686 void omap_clk_canidle(struct clk *clk, int can) in omap_clk_canidle() argument
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A Dnpcm7xx_clk.c124 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
231 npcm7xx_clk_update_all_plls(clk); in npcm7xx_clk_update_all_clocks()
232 npcm7xx_clk_update_all_sels(clk); in npcm7xx_clk_update_all_clocks()
233 npcm7xx_clk_update_all_dividers(clk); in npcm7xx_clk_update_all_clocks()
641 pll->clk = clk; in npcm7xx_init_clock_pll()
655 sel->clk = clk; in npcm7xx_init_clock_sel()
670 div->clk = clk; in npcm7xx_init_clock_divider()
691 return clk->clkref; in npcm7xx_get_clock()
693 return clk->plls[index].clock_out; in npcm7xx_get_clock()
695 return clk->sels[index].clock_out; in npcm7xx_get_clock()
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A Dstm32l4x5_syscfg.c231 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); in stm32l4x5_syscfg_init()
237 if (!clock_has_source(s->clk)) { in stm32l4x5_syscfg_realize()
257 VMSTATE_CLOCK(clk, Stm32l4x5SyscfgState),
/qemu/include/hw/
A Dclock.h114 void clock_setup_canonical_path(Clock *clk);
150 void clock_clear_callback(Clock *clk);
176 return clk->source != NULL; in clock_has_source()
210 void clock_propagate(Clock *clk);
223 if (clock_set(clk, value)) { in clock_update()
224 clock_propagate(clk); in clock_update()
246 return clk->period; in clock_get()
323 if (clk->period == 0) { in clock_ns_to_ticks()
327 divu128(&lo, &hi, clk->period); in clock_ns_to_ticks()
339 return clock_get(clk) != 0; in clock_is_enabled()
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/qemu/include/hw/arm/
A Domap.h49 typedef struct clk *omap_clk;
52 void omap_clk_adduser(struct clk *clk, qemu_irq user);
53 void omap_clk_get(omap_clk clk);
54 void omap_clk_put(omap_clk clk);
55 void omap_clk_onoff(omap_clk clk, int on);
56 void omap_clk_canidle(omap_clk clk, int can);
58 int64_t omap_clk_getrate(omap_clk clk);
59 void omap_clk_reparent(omap_clk clk, omap_clk parent);
90 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
91 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
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/qemu/hw/arm/
A Domap1.c108 omap_clk clk; member
285 s->clk = clk; in omap_mpu_timer_init()
414 s->timer.clk = clk; in omap_wd_timer_init()
520 s->timer.clk = clk; in omap_os_timer_init()
1910 int clk; member
2103 s->clk = 1; in omap_mpuio_reset()
2328 int clk; member
2397 s->clk = 1; in omap_pwl_reset()
2521 s->clk = clk; in omap_pwt_init()
3519 int clk; member
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A Dnpcm7xx.c422 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); in npcm7xx_init()
532 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); in npcm7xx_realize()
533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); in npcm7xx_realize()
548 DEVICE(&s->clk), "adc-clock")); in npcm7xx_realize()
564 DEVICE(&s->clk), "timer-clock")); in npcm7xx_realize()
581 qdev_get_gpio_in_named(DEVICE(&s->clk), in npcm7xx_realize()
648 DEVICE(&s->clk), "apb3-clock")); in npcm7xx_realize()
660 qdev_get_clock_out(DEVICE(&s->clk), in npcm7xx_realize()
A Dmps3r.c118 Clock *clk; member
362 mms->clk = clock_new(OBJECT(machine), "CLK"); in mps3r_common_init()
363 clock_set_hz(mms->clk, CLK_FRQ); in mps3r_common_init()
465 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); in mps3r_common_init()
473 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); in mps3r_common_init()
/qemu/hw/gpio/
A Domap_gpio.c49 void *clk; member
218 if (!s->clk) { in omap_gpio_realize()
223 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) in omap_gpio_set_clk() argument
225 gpio->clk = clk; in omap_gpio_set_clk()
A Dstm32l4x5_gpio.c253 uint32_t clock_freq_hz = clock_get_hz(s->clk); in clock_freq_get()
410 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); in stm32l4x5_gpio_init()
422 if (!clock_has_source(s->clk)) { in stm32l4x5_gpio_realize()
445 VMSTATE_CLOCK(clk, Stm32l4x5GpioState),
/qemu/include/hw/ppc/
A Dppc.h18 static inline void clk_setup (clk_setup_t *clk, uint32_t freq) in clk_setup() argument
20 if (clk->cb != NULL) in clk_setup()
21 (*clk->cb)(clk->opaque, freq); in clk_setup()
/qemu/include/hw/misc/
A Dnpcm7xx_clk.h97 NPCM7xxCLKState *clk; member
118 NPCM7xxCLKState *clk; member
143 NPCM7xxCLKState *clk; member
/qemu/hw/ssi/
A Dbcm2835_spi.c121 readval = s->clk & 0xffff; in bcm2835_spi_read()
200 s->clk = value & 0xffff; in bcm2835_spi_write()
245 s->clk = 0; in bcm2835_spi_reset()
259 VMSTATE_UINT32(clk, BCM2835SPIState),
/qemu/hw/timer/
A Dsse-counter.c127 return s->ns_then + clock_ticks_to_ns(s->clk, tick); in sse_counter_tick_to_time()
150 ticks = clock_ns_to_ticks(s->clk, now - s->ns_then); in sse_counter_for_timestamp()
421 s->clk = qdev_init_clock_in(DEVICE(obj), "CLK", sse_clk_callback, s, in sse_counter_init()
435 if (!clock_has_source(s->clk)) { in sse_counter_realize()
446 VMSTATE_CLOCK(clk, SSECounter),
A Dstellaris-gptm.c43 tick += clock_ticks_to_ns(s->clk, count); in gptm_reload()
267 VMSTATE_CLOCK(clk, gptm_state),
295 s->clk = qdev_init_clock_in(dev, "clk", NULL, NULL, 0); in stellaris_gptm_init()
302 if (!clock_has_source(s->clk)) { in stellaris_gptm_realize()
/qemu/hw/char/
A Dpl011.c346 uint64_t clk; in pl011_get_baudrate() local
352 clk = clock_get_hz(s->clk); in pl011_get_baudrate()
353 return (clk / ((s->ibrd << 6) + s->fbrd)) << 2; in pl011_get_baudrate()
359 clock_get_hz(s->clk), in pl011_trace_baudrate_change()
544 VMSTATE_CLOCK(clk, PL011State),
624 s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s, in pl011_init()
/qemu/hw/intc/
A Domap_intc.c368 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_iclk() argument
370 intc->iclk = clk; in omap_intc_set_iclk()
373 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_fclk() argument
375 intc->fclk = clk; in omap_intc_set_fclk()
/qemu/hw/input/
A Dpl050.c35 VMSTATE_UINT32(clk, PL050State),
108 return s->clk; in pl050_read()
139 s->clk = value; in pl050_write()
/qemu/hw/i2c/
A Domap_i2c.c504 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk) in omap_i2c_set_iclk() argument
506 i2c->iclk = clk; in omap_i2c_set_iclk()
509 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk) in omap_i2c_set_fclk() argument
511 i2c->fclk = clk; in omap_i2c_set_fclk()
/qemu/hw/sd/
A Domap_mmc.c33 omap_clk clk; member
589 qemu_irq irq, qemu_irq dma[], omap_clk clk) in omap_mmc_init() argument
595 s->clk = clk; in omap_mmc_init()
/qemu/docs/devel/
A Dclocks.rst206 Clock *clk = qdev_get_clock_in(DEVICE(mydev), "clk_in");
212 Clock *clk = qdev_get_clock_out(DEVICE(mydev), "clk_out");
302 clk = qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback,
305 clock_set_ns(clk, 10);
312 if (!clock_has_source(s->clk)) {
313 error_setg(errp, "MyDevice: clk input must be connected");
467 qdev_alias_clock(B, "clk", A, "b_clk");
470 * the clock "clk" of its child B.
486 >>"b_clk">>>| "clk" | | |
510 Clock *clk;
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