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/qemu/docs/devel/
A Dclocks.rst1 Modelling a clock tree in QEMU
11 configuration errors in the clock tree such as badly configured PLL, clock
53 The clock state
63 the current period of a clock to be fetched at any time. When a clock
76 Adding a new clock
114 * callback for the input clock (see "Callback on input clock
224 device clock. For example, to connect the input clock ``clk2`` of
232 input clock, even another input clock. The following diagram shows
320 zero. You should use the clock callback to find out when the clock
442 ``clock_propagate()`` on the clock. Thus, setting the clock value can
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A Dreplay.rst85 non-determinism. These are inputs from clock and peripheral devices,
103 Two other checkpoints govern the "warping" of the virtual clock.
104 While the virtual machine is idle, the virtual clock increments at
106 (called the warp timer) on the virtual real time clock, so that the
107 timer fires at the next deadline of the virtual clock; the virtual clock
134 clock and timers does not affect deterministic replay at all.
138 * Host clock. This clock is used by device models that simulate real time
139 sources (e.g. real time clock chip). Host clock is the one of the sources
142 * Virtual real time clock. This clock is similar to real time clock but
154 but its speed depends on the guest execution. This clock is used by
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/qemu/util/
A Dqemu-timer.c67 QEMUClock *clock; member
105 timer_list->clock = clock; in timerlist_new()
116 if (timer_list->clock) { in timerlist_free()
130 clock->type = type; in qemu_clock_init()
132 QLIST_INIT(&clock->timerlists); in qemu_clock_init()
161 bool old = clock->enabled; in qemu_clock_enable()
162 clock->enabled = enabled; in qemu_clock_enable()
221 if (!timer_list->clock->enabled) { in timerlist_deadline_ns()
259 if (!clock->enabled) { in qemu_clock_deadline_ns_all()
504 if (!timer_list->clock->enabled) { in timerlist_run_timers()
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/qemu/hw/core/
A Dqdev-clock.c62 (Object **) &ncl->clock, in qdev_init_clocklist()
74 ncl->clock = clk; in qdev_init_clocklist()
94 clock_clear_callback(ncl->clock); in qdev_finalize_clocklist()
95 object_unref(OBJECT(ncl->clock)); in qdev_finalize_clocklist()
110 return ncl->clock; in qdev_init_clock_out()
124 clock_set_callback(ncl->clock, callback, opaque, events); in qdev_init_clock_in()
126 return ncl->clock; in qdev_init_clock_in()
174 return ncl->clock; in qdev_get_clock_in()
191 return ncl->clock; in qdev_get_clock_out()
203 qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock); in qdev_alias_clock()
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A Dmeson.build11 'clock.c',
12 'qdev-clock.c',
47 'clock-vmstate.c',
/qemu/include/sysemu/
A Dreplay.h79 int64_t replay_save_clock(ReplayClockKind kind, int64_t clock,
84 #define REPLAY_CLOCK(clock, value) \ argument
87 ? replay_read_clock((clock), icount_get_raw()) \
89 ? replay_save_clock((clock), (value), icount_get_raw()) \
91 #define REPLAY_CLOCK_LOCKED(clock, value) \ argument
94 ? replay_read_clock((clock), icount_get_raw_locked()) \
96 ? replay_save_clock((clock), (value), icount_get_raw_locked()) \
/qemu/replay/
A Dreplay-time.c17 int64_t replay_save_clock(ReplayClockKind kind, int64_t clock, in replay_save_clock() argument
29 replay_put_qword(clock); in replay_save_clock()
31 return clock; in replay_save_clock()
40 int64_t clock = replay_get_qword(); in replay_read_next_clock() local
45 replay_state.cached_clock[read_kind] = clock; in replay_read_next_clock()
/qemu/hw/timer/
A Dpxa2xx_timer.c83 int32_t clock; member
95 int32_t clock; member
123 now_vm = s->clock + in pxa2xx_timer_update()
226 return s->tm4[tm].clock; in pxa2xx_timer_read()
227 return s->tm4[tm].clock + in pxa2xx_timer_read()
309 s->oldclock = s->clock; in pxa2xx_timer_write()
311 s->clock = value; in pxa2xx_timer_write()
333 s->tm4[tm].clock = value; in pxa2xx_timer_write()
430 t->clock = 0; in pxa2xx_timer_tick4()
460 s->clock = 0; in pxa2xx_timer_init()
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/qemu/hw/i386/kvm/
A Dclock.c41 uint64_t clock; member
111 s->clock = data.clock; in kvm_update_clock()
183 s->clock = pvclock_via_mem; in kvmclock_vm_state_change()
189 data.clock = s->clock; in kvmclock_vm_state_change()
299 VMSTATE_UINT64(clock, KVMClockState),
/qemu/accel/tcg/
A Dicount-common.c251 int64_t clock = REPLAY_CLOCK_LOCKED(REPLAY_CLOCK_VIRTUAL_RT, in icount_warp_rt() local
255 warp_delta = clock - timers_state.vm_clock_warp_start; in icount_warp_rt()
263 int64_t delta = clock - cur_icount; in icount_warp_rt()
293 int64_t clock; in icount_start_warp_timer() local
334 clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); in icount_start_warp_timer()
379 || timers_state.vm_clock_warp_start > clock) { in icount_start_warp_timer()
380 timers_state.vm_clock_warp_start = clock; in icount_start_warp_timer()
385 clock + deadline); in icount_start_warp_timer()
/qemu/hw/misc/
A Dimx_ccm.c31 uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx_ccm_get_clock_frequency() argument
37 freq = klass->get_clock_frequency(dev, clock); in imx_ccm_get_clock_frequency()
40 DPRINTF("(clock = %d) = %u\n", clock, freq); in imx_ccm_get_clock_frequency()
A Dimx25_ccm.c168 static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx25_ccm_get_clock_frequency() argument
171 DPRINTF("Clock = %d)\n", clock); in imx25_ccm_get_clock_frequency()
173 switch (clock) { in imx25_ccm_get_clock_frequency()
185 TYPE_IMX25_CCM, __func__, clock); in imx25_ccm_get_clock_frequency()
189 DPRINTF("Clock = %d) = %u\n", clock, freq); in imx25_ccm_get_clock_frequency()
A Dimx7_ccm.c223 static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx7_ccm_get_clock_frequency() argument
235 switch (clock) { in imx7_ccm_get_clock_frequency()
252 TYPE_IMX7_CCM, __func__, clock); in imx7_ccm_get_clock_frequency()
256 TYPE_IMX7_CCM, __func__, clock); in imx7_ccm_get_clock_frequency()
260 trace_ccm_clock_freq(clock, freq); in imx7_ccm_get_clock_frequency()
A Dimx31_ccm.c184 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx31_ccm_get_clock_frequency() argument
188 switch (clock) { in imx31_ccm_get_clock_frequency()
200 TYPE_IMX31_CCM, __func__, clock); in imx31_ccm_get_clock_frequency()
204 DPRINTF("Clock = %d) = %u\n", clock, freq); in imx31_ccm_get_clock_frequency()
A Dnpcm7xx_mft.c156 Clock *clock, uint32_t max_rpm, uint32_t duty, uint16_t tgt, in npcm7xx_mft_compute_cnt() argument
175 count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) / in npcm7xx_mft_compute_cnt()
201 trace_npcm7xx_mft_rpm(clock->canonical_path, clock_get_hz(clock), in npcm7xx_mft_compute_cnt()
/qemu/pc-bios/
A Dbamboo.dts34 clock-frequency = <0x1fca0550>;
75 clock-frequency = <0x07f28154>;
98 clock-frequency = <0x03f940aa>;
105 clock-frequency = <0x03f940aa>;
115 clock-frequency = <0x00a8c000>;
126 clock-frequency = <0x00a8c000>;
/qemu/hw/net/can/
A Dcan_sja1000.c70 s->clock = 0x00; in can_sja_hardware_reset()
154 if (s->clock & 0x80) { /* PeliCAN Mode */ in can_sja_accept_filter()
437 if (s->clock & 0x80) { /* PeliCAN Mode */ in can_sja_mem_write()
558 s->clock = val; in can_sja_mem_write()
652 s->clock = val; in can_sja_mem_write()
668 if (s->clock & 0x80) { /* PeliCAN Mode */ in can_sja_mem_read()
715 temp = s->clock; in can_sja_mem_read()
746 temp = s->clock; in can_sja_mem_read()
763 if (s->clock & 0x80) { /* PeliCAN Mode */ in can_sja_can_receive()
799 if (s->clock & 0x80) { /* PeliCAN Mode */ in can_sja_receive()
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/qemu/hw/ppc/
A Dppc.c498 static uint64_t ns_to_tb(uint32_t freq, int64_t clock) in ns_to_tb() argument
500 return muldiv64(clock, freq, NANOSECONDS_PER_SECOND); in ns_to_tb()
563 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in cpu_ppc_store_tbl() local
566 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); in cpu_ppc_store_tbl()
574 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in _cpu_ppc_store_tbu() local
577 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); in _cpu_ppc_store_tbu()
579 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, in _cpu_ppc_store_tbu()
615 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in cpu_ppc_store_atbl() local
626 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in cpu_ppc_store_atbu() local
631 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, in cpu_ppc_store_atbu()
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/qemu/system/
A Drtc.c49 static time_t qemu_ref_timedate(QEMUClockType clock) in qemu_ref_timedate() argument
51 time_t value = qemu_clock_get_ms(clock) / 1000; in qemu_ref_timedate()
52 switch (clock) { in qemu_ref_timedate()
/qemu/hw/display/
A Dedid-generate.c60 uint64_t clock; member
75 timings->clock = ((uint64_t)refresh_rate * in generate_timings()
262 stw_le_p(desc, timings->clock); in edid_desc_timing()
362 did[8] = timings->clock & 0xff; in qemu_displayid_generate()
363 did[9] = (timings->clock & 0xff00) >> 8; in qemu_displayid_generate()
364 did[10] = (timings->clock & 0xff0000) >> 16; in qemu_displayid_generate()
418 if (info->prefx >= 4096 || info->prefy >= 4096 || timings.clock >= 65536) { in qemu_edid_generate()
/qemu/hw/mips/
A Dcps.c41 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); in mips_cps_init()
71 if (!clock_get(s->clock)) { in mips_cps_realize()
88 qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); in mips_cps_realize()
/qemu/hw/audio/
A Dfmopl.c728 OPL->freqbase = (OPL->rate) ? ((double)OPL->clock / OPL->rate) / 72 : 0; in OPL_initialize()
730 OPL->TimerBase = 1.0/((double)OPL->clock / 72.0 ); in OPL_initialize()
739 …OPL->amsIncr = OPL->rate ? (double)AMS_ENT*(1<<AMS_SHIFT) / OPL->rate * 3.7 * ((double)OPL->clock/… in OPL_initialize()
740 …OPL->vibIncr = OPL->rate ? (double)VIB_ENT*(1<<VIB_SHIFT) / OPL->rate * 6.4 * ((double)OPL->clock/… in OPL_initialize()
1073 FM_OPL *OPLCreate(int clock, int rate) in OPLCreate() argument
1092 OPL->clock = clock; in OPLCreate()
1110 clock&0xff, in OPLCreate()
1111 (clock/0x100)&0xff, in OPLCreate()
1112 (clock/0x10000)&0xff, in OPLCreate()
1113 (clock/0x1000000)&0xff); in OPLCreate()
A Dfmopl.h58 int clock; /* master clock (Hz) */ member
93 FM_OPL *OPLCreate(int clock, int rate);
/qemu/hw/adc/
A Dnpcm7xx_adc.c90 npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, in npcm7xx_adc_start_convert()
241 s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL, 0); in npcm7xx_adc_init()
260 VMSTATE_CLOCK(clock, NPCM7xxADCState),
/qemu/hw/sd/
A Dpl181.c35 uint32_t clock; member
67 VMSTATE_UINT32(clock, PL181State),
305 return s->clock; in pl181_read()
386 s->clock = value & 0xff; in pl181_write()

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