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Searched refs:control (Results 1 – 25 of 235) sorted by relevance

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/qemu/hw/timer/
A Darm_mptimer.c74 if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { in timerblock_set_count()
84 if ((control & 1) && ((control & 0xff00) || load != 0)) { in timerblock_run()
85 ptimer_run(timer, !(control & 2)); in timerblock_run()
95 if ((tb->control & 2) && (tb->control & 0xff00) == 0 && in timerblock_tick()
113 return tb->control; in timerblock_read()
125 uint32_t control = tb->control; in timerblock_write() local
132 if ((control & 1) && (control & 0xff00) == 0 && value == 0) { in timerblock_write()
144 if ((control & 1) && (control & 0xff00) == 0 && value == 0 && in timerblock_write()
154 if ((control & 3) != (value & 3)) { in timerblock_write()
168 tb->control = value; in timerblock_write()
[all …]
A Da9gtimer.c92 if ((s->control & R_CONTROL_TIMER_ENABLE) && in a9_gtimer_update()
123 if (s->control & R_CONTROL_TIMER_ENABLE) { in a9_gtimer_update()
157 ret = s->control | gtb->control; in a9_gtimer_read()
200 if (s->control & R_CONTROL_TIMER_ENABLE) { in a9_gtimer_write()
208 gtb->control = value & R_CONTROL_BANKED; in a9_gtimer_write()
209 s->control = value & ~R_CONTROL_BANKED; in a9_gtimer_write()
285 s->control = 0; in a9_gtimer_reset()
290 gtb->control = 0; in a9_gtimer_reset()
329 return s->control != 0; in vmstate_a9_gtimer_control_needed()
337 VMSTATE_UINT32(control, A9GTimerPerCPU),
[all …]
A Darmv7m_systick.c39 if (s->control & SYSTICK_CLKSOURCE) { in systick_set_period_from_clock()
52 s->control |= SYSTICK_COUNTFLAG; in systick_timer_tick()
53 if (s->control & SYSTICK_TICKINT) { in systick_timer_tick()
79 val = s->control; in systick_read()
80 s->control &= ~SYSTICK_COUNTFLAG; in systick_read()
148 oldval = s->control; in systick_write()
149 s->control &= 0xfffffff8; in systick_write()
150 s->control |= value & 7; in systick_write()
182 s->control &= ~SYSTICK_COUNTFLAG; in systick_write()
205 s->control = 0; in systick_reset()
[all …]
A Dcmsdk-apb-dualtimer.c112 switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_divisor()
135 changed = m->control ^ newctrl; in cmsdk_dualtimermod_write_control()
176 if (!(m->control & R_CONTROL_SIZE_MASK)) { in cmsdk_dualtimermod_write_control()
182 if (!(m->control & R_CONTROL_SIZE_MASK)) { in cmsdk_dualtimermod_write_control()
233 m->control = newctrl; in cmsdk_dualtimermod_write_control()
273 if (m->control & R_CONTROL_MODE_MASK) { in cmsdk_apb_dualtimer_read()
289 if (!(m->control & R_CONTROL_SIZE_MASK)) { in cmsdk_apb_dualtimer_read()
294 r = m->control; in cmsdk_apb_dualtimer_read()
350 if (!(m->control & R_CONTROL_SIZE_MASK)) { in cmsdk_apb_dualtimer_write()
354 if (!(m->control & R_CONTROL_MODE_MASK)) { in cmsdk_apb_dualtimer_write()
[all …]
A Darm_timer.c34 uint32_t control; member
46 if (s->int_level && (s->control & TIMER_CTRL_IE)) { in arm_timer_update()
64 return s->control; in arm_timer_read()
68 if ((s->control & TIMER_CTRL_IE) == 0) in arm_timer_read()
88 if (s->control & TIMER_CTRL_32BIT) in arm_timer_recalibrate()
118 if (s->control & TIMER_CTRL_ENABLE) { in arm_timer_write()
124 s->control = value; in arm_timer_write()
131 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); in arm_timer_write()
133 if (s->control & TIMER_CTRL_ENABLE) { in arm_timer_write()
167 VMSTATE_UINT32(control, arm_timer_state),
[all …]
A Dallwinner-a10-pit.c52 return s->control[index]; in a10_pit_read()
87 prescaler = 1 << extract32(s->control[index], 4, 3); in a10_pit_set_freq()
88 source = extract32(s->control[index], 2, 2); in a10_pit_set_freq()
120 s->control[index] = value; in a10_pit_write()
123 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { in a10_pit_write()
126 if (s->control[index] & AW_A10_PIT_TIMER_EN) { in a10_pit_write()
128 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { in a10_pit_write()
229 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; in a10_pit_reset()
250 if (s->control[i] & AW_A10_PIT_TIMER_EN) { in a10_pit_timer_cb()
252 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { in a10_pit_timer_cb()
[all …]
A Ddigic-timer.c44 VMSTATE_UINT32(control, DigicTimerState),
57 s->control = 0; in digic_timer_reset()
68 ret = s->control; in digic_timer_read()
102 s->control = (uint32_t)value; in digic_timer_write()
A Dstellaris-gptm.c69 if ((s->control & 0x20)) { in gptm_tick()
75 s->control &= ~1; in gptm_tick()
114 return s->control; in gptm_read()
180 oldval = s->control; in gptm_write()
181 s->control = value; in gptm_write()
256 VMSTATE_UINT32(control, gptm_state),
/qemu/hw/i2c/
A Domap_i2c.c51 uint16_t control; member
77 if ((s->control >> 2) & 1) { /* RM */ in omap_i2c_fifo_run()
78 if ((s->control >> 1) & 1) { /* STP */ in omap_i2c_fifo_run()
80 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
95 if ((s->control >> 9) & 1) { /* TRX */ in omap_i2c_fifo_run()
135 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
150 s->control = 0; in omap_i2c_reset()
199 if (s->control & (1 << 14)) { /* BE */ in omap_i2c_read()
233 return s->control; in omap_i2c_read()
310 if (s->control & (1 << 14)) { /* BE */ in omap_i2c_write()
[all …]
/qemu/hw/char/
A Dparallel.c119 s->control = val; in parallel_ioport_write_sw()
152 if (s->control == val) in parallel_ioport_write_hw()
167 s->control = val; in parallel_ioport_write_hw()
259 if (s->control & PARA_CTR_DIR) in parallel_ioport_read_sw()
280 ret = s->control; in parallel_ioport_read_sw()
311 if (s->control == 0) { in parallel_ioport_read_hw()
315 s->control = ret; in parallel_ioport_read_hw()
318 ret = s->control; in parallel_ioport_read_hw()
442 s->control = PARA_CTR_SELECT; in parallel_reset()
443 s->control |= PARA_CTR_INIT; in parallel_reset()
[all …]
A Dgrlib_apbuart.c91 uint32_t control; member
150 if (uart->control & UART_RECEIVE_ENABLE) { in grlib_apbuart_receive()
155 if (uart->control & UART_RECEIVE_INTERRUPT) { in grlib_apbuart_receive()
185 return uart->control; in grlib_apbuart_read()
211 (uart->control & UART_TRANSMIT_ENABLE)) { in grlib_apbuart_write()
217 if (uart->control & UART_TRANSMIT_INTERRUPT) { in grlib_apbuart_write()
228 uart->control = value; in grlib_apbuart_write()
274 uart->control = 0; in grlib_apbuart_reset()
/qemu/hw/misc/
A Dallwinner-sid.c53 val = s->control; in allwinner_sid_read()
78 s->control = val; in allwinner_sid_write()
80 if ((s->control & REG_PRCTL_OP_LOCK) && in allwinner_sid_write()
81 (s->control & REG_PRCTL_WRITE)) { in allwinner_sid_write()
82 uint32_t id = s->control >> 16; in allwinner_sid_write()
88 s->control &= ~REG_PRCTL_WRITE; in allwinner_sid_write()
115 s->control = 0; in allwinner_sid_reset()
140 VMSTATE_UINT32(control, AwSidState),
A Da9scu.c27 return s->control; in a9_scu_read()
55 s->control = value & 1; in a9_scu_write()
97 s->control = 0; in a9_scu_reset()
120 VMSTATE_UINT32(control, A9SCUState),
/qemu/target/arm/tcg/
A Dtranslate-m-nocp.c134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM()
381 TCGv_i32 sfpa, control; in gen_M_fp_sysreg_write() local
389 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
390 tcg_gen_deposit_i32(control, control, sfpa, in gen_M_fp_sysreg_write()
392 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
474 TCGv_i32 control, sfpa, fpscr; in gen_M_fp_sysreg_read() local
480 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_read()
493 tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); in gen_M_fp_sysreg_read()
494 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_read()
502 TCGv_i32 control, sfpa, fpscr, fpdscr; in gen_M_fp_sysreg_read() local
[all …]
A Dm_helper.c64 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
198 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
470 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
471 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
649 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; in HELPER()
970 env->v7m.control[M_REG_S] &= in v7m_exception_taken()
1172 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; in HELPER()
1836 env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], in do_v7m_exception_exit()
1870 env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], in do_v7m_exception_exit()
2161 !(env->v7m.control[M_REG_S] & 1)) { in v7m_handle_execute_nsc()
[all …]
/qemu/hw/arm/
A Dbcm2836.c40 object_initialize_child(obj, "control", &s->control, in bcm283x_base_init()
120 if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { in bcm2836_realize()
124 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); in bcm2836_realize()
127 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); in bcm2836_realize()
129 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0)); in bcm2836_realize()
149 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n, in bcm2836_realize()
151 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n, in bcm2836_realize()
156 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n)); in bcm2836_realize()
158 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n)); in bcm2836_realize()
160 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n)); in bcm2836_realize()
[all …]
/qemu/target/i386/kvm/
A Dhyperv.c65 env->msr_hv_synic_control = exit->u.synic.control; in kvm_hv_handle_exit()
124 uint64_t control = exit->u.syndbg.control; in kvm_hv_handle_exit() local
125 env->msr_hv_syndbg_control = control; in kvm_hv_handle_exit()
129 if (control & HV_SYNDBG_CONTROL_SEND) { in kvm_hv_handle_exit()
132 HV_SYNDBG_CONTROL_SEND_SIZE(control)); in kvm_hv_handle_exit()
133 } else if (control & HV_SYNDBG_CONTROL_RECV) { in kvm_hv_handle_exit()
/qemu/target/i386/tcg/sysemu/
A Dsvm_helper.c141 control.lbr_ctl)); in virtual_vm_load_save_enabled()
239 control.intercept)); in helper_vmrun()
259 offsetof(struct vmcb, control.int_state)) & in helper_vmrun()
267 control.asid)); in helper_vmrun()
271 control.msrpm_base_pa)); in helper_vmrun()
307 offsetof(struct vmcb, control.tsc_offset)); in helper_vmrun()
415 control.event_inj)); in helper_vmrun()
667 control.msrpm_base_pa)); in cpu_svm_check_intercept_param()
737 control.exit_info_2)), in cpu_vmexit()
903 control.event_inj))); in do_vmexit()
[all …]
/qemu/hw/dma/
A Dxlnx_dpdma.c136 uint32_t control; member
222 return (desc->control & DSCR_CTRL_ENABLE_CRC) != 0; in xlnx_dpdma_desc_crc_enabled()
259 return (desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0; in xlnx_dpdma_desc_update_enabled()
274 return (desc->control & DSCR_CTRL_IGNORE_DONE) != 0; in xlnx_dpdma_desc_ignore_done_bit()
361 if ((desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0) { in xlnx_dpdma_update_desc_info()
367 if ((desc->control & DSCR_CTRL_IGNORE_DONE) != 0) { in xlnx_dpdma_update_desc_info()
373 if ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0) { in xlnx_dpdma_update_desc_info()
376 if ((desc->control & DSCR_CTRL_ENABLE_CRC) != 0) { in xlnx_dpdma_update_desc_info()
382 if ((desc->control & DSCR_CTRL_AXI_BURST_TYPE) != 0) { in xlnx_dpdma_update_desc_info()
629 desc->control = le32_to_cpu(desc->control); in xlnx_dpdma_read_descriptor()
[all …]
A Dsifive_pdma.c113 s->chan[ch].control &= ~CONTROL_DONE; in sifive_pdma_run()
114 s->chan[ch].control &= ~CONTROL_ERR; in sifive_pdma_run()
148 s->chan[ch].control &= ~CONTROL_RUN; in sifive_pdma_run()
149 s->chan[ch].control |= CONTROL_DONE; in sifive_pdma_run()
154 s->chan[ch].control |= CONTROL_ERR; in sifive_pdma_run()
162 done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE); in sifive_pdma_update_irq()
163 err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE); in sifive_pdma_update_irq()
221 val = s->chan[ch].control; in sifive_pdma_readl()
339 run = !!(s->chan[ch].control & CONTROL_RUN); in sifive_pdma_writel()
355 s->chan[ch].control = value; in sifive_pdma_writel()
[all …]
/qemu/hw/watchdog/
A Dcmsdk-apb-watchdog.c88 return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK); in cmsdk_apb_watchdog_intstatus()
94 return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK); in cmsdk_apb_watchdog_resetstatus()
134 r = s->control; in cmsdk_apb_watchdog_read()
205 uint32_t prev_control = s->control; in cmsdk_apb_watchdog_write()
206 if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { in cmsdk_apb_watchdog_write()
214 s->control = value & R_WDOGCONTROL_VALID_MASK; in cmsdk_apb_watchdog_write()
215 if (R_WDOGCONTROL_INTEN_MASK & (s->control ^ prev_control)) { in cmsdk_apb_watchdog_write()
217 if (R_WDOGCONTROL_INTEN_MASK & s->control) { in cmsdk_apb_watchdog_write()
314 s->control = 0; in cmsdk_apb_watchdog_reset()
387 VMSTATE_UINT32(control, CMSDKAPBWatchdog),
/qemu/hw/net/
A Dtulip.c138 desc->control & 0x7ff, (desc->control >> 11) & 0x7ff, in tulip_dump_tx_descriptor()
147 desc->control & 0x7ff, (desc->control >> 11) & 0x7ff, in tulip_dump_rx_descriptor()
154 if (desc->control & RDES1_RER) { in tulip_next_rx_descriptor()
156 } else if (desc->control & RDES1_RCH) { in tulip_next_rx_descriptor()
573 if (desc->control & TDES1_IC) { in tulip_tx()
647 if (desc->control & TDES1_IC) { in tulip_setup_frame()
656 if (desc->control & TDES1_TER) { in tulip_next_tx_descriptor()
658 } else if (desc->control & TDES1_TCH) { in tulip_next_tx_descriptor()
693 if (desc.control & TDES1_SET) { in tulip_xmit_list_update()
696 if (desc.control & TDES1_FS) { in tulip_xmit_list_update()
[all …]
/qemu/pc-bios/optionrom/
A Doptrom_fw_cfg.h55 uint32_t control = (entry << 16) | FW_CFG_DMA_CTL_SELECT in bios_cfg_read_entry_dma() local
60 access.control = cpu_to_be32(control); in bios_cfg_read_entry_dma()
66 while (be32_to_cpu(access.control) & ~FW_CFG_DMA_CTL_ERROR) { in bios_cfg_read_entry_dma()
/qemu/hw/input/
A Dlasips2.c43 VMSTATE_UINT8(control, LASIPS2Port),
162 lp->control = val; in lasips2_reg_write()
166 if (lp->control & LASIPS2_CONTROL_LOOPBACK) { in lasips2_reg_write()
201 if (lp->control & LASIPS2_CONTROL_LOOPBACK) { in lasips2_reg_read()
212 ret = lp->control; in lasips2_reg_read()
218 if (lp->control & LASIPS2_CONTROL_DIAG) { in lasips2_reg_read()
219 if (!(lp->control & LASIPS2_CONTROL_DATDIR)) { in lasips2_reg_read()
223 if (!(lp->control & LASIPS2_CONTROL_CLKDIR)) { in lasips2_reg_read()
228 if (lp->control & LASIPS2_CONTROL_LOOPBACK) { in lasips2_reg_read()
/qemu/pc-bios/s390-ccw/
A Dscsi.h109 uint8_t control; /* b5 */ member
119 uint8_t control; member
126 uint8_t control; member
137 uint8_t control; member
154 uint8_t control; member

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