Home
last modified time | relevance | path

Searched refs:ctrl (Results 1 – 25 of 141) sorted by relevance

123456

/qemu/target/riscv/
A Ddebug.c487 if (ctrl & TYPE2_EXEC) { in type2_breakpoint_insert()
491 if (ctrl & TYPE2_LOAD) { in type2_breakpoint_insert()
494 if (ctrl & TYPE2_STORE) { in type2_breakpoint_insert()
584 size = extract32(ctrl, 16, 4); in type6_mcontrol6_validate()
612 if (ctrl & TYPE6_EXEC) { in type6_breakpoint_insert()
616 if (ctrl & TYPE6_LOAD) { in type6_breakpoint_insert()
620 if (ctrl & TYPE6_STORE) { in type6_breakpoint_insert()
949 target_ulong ctrl; in riscv_cpu_debug_check_breakpoint() local
995 target_ulong ctrl; in riscv_cpu_debug_check_watchpoint() local
1010 ctrl = env->tdata1[i]; in riscv_cpu_debug_check_watchpoint()
[all …]
/qemu/hw/usb/
A Dhcd-uhci.c327 port->ctrl = 0x0080; in uhci_reset()
521 val = port->ctrl; in uhci_port_read()
601 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { in uhci_wakeup()
629 le32_to_cpus(&td->ctrl); in uhci_read_td()
642 td->ctrl |= TD_CTRL_NAK; in uhci_handle_td_error()
668 td->ctrl &= ~TD_CTRL_ACTIVE; in uhci_handle_td_error()
670 if (td->ctrl & TD_CTRL_IOC) { in uhci_handle_td_error()
685 if (td->ctrl & TD_CTRL_IOS) in uhci_complete_td()
694 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); in uhci_complete_td()
700 if (td->ctrl & TD_CTRL_IOC) in uhci_complete_td()
[all …]
A Dhcd-ohci.c330 port->ctrl = 0; in ohci_roothub_reset()
1456 if (ohci->rhport[i].ctrl & val) { in ohci_port_set_if_connected()
1460 ohci->rhport[i].ctrl |= val; in ohci_port_set_if_connected()
1472 old_state = port->ctrl; in ohci_port_set_status()
1479 port->ctrl &= ~OHCI_PORT_PES; in ohci_port_set_status()
1502 if (old_state != port->ctrl) { in ohci_port_set_status()
1780 uint32_t old_state = port->ctrl; in ohci_attach()
1799 if (old_state != port->ctrl) { in ohci_attach()
1820 uint32_t old_state = port->ctrl; in ohci_detach()
1827 port->ctrl |= OHCI_PORT_CSC; in ohci_detach()
[all …]
/qemu/hw/block/
A Dswim.c252 drive->swimctrl = bus->ctrl; in swim_drive_realize()
474 SWIMCtrl *ctrl = &sys->ctrl; in sysbus_swim_reset() local
477 ctrl->mode = 0; in sysbus_swim_reset()
478 ctrl->iwm_switch = 0; in sysbus_swim_reset()
479 memset(ctrl->iwmregs, 0, sizeof(ctrl->iwmregs)); in sysbus_swim_reset()
481 ctrl->swim_phase = 0; in sysbus_swim_reset()
482 ctrl->swim_mode = 0; in sysbus_swim_reset()
483 memset(ctrl->ismregs, 0, sizeof(ctrl->ismregs)); in sysbus_swim_reset()
493 SWIMCtrl *swimctrl = &sbs->ctrl; in sysbus_swim_init()
506 SWIMCtrl *swimctrl = &sys->ctrl; in sysbus_swim_realize()
[all …]
/qemu/pc-bios/s390-ccw/
A Dcio.c189 if (irb->scsw.ctrl & SCSW_FCTL_START_FUNC) { in print_irb_err()
192 if (irb->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { in print_irb_err()
195 if (irb->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { in print_irb_err()
205 if (irb->scsw.ctrl & SCSW_ACTL_START_PEND) { in print_irb_err()
208 if (irb->scsw.ctrl & SCSW_ACTL_HALT_PEND) { in print_irb_err()
214 if (irb->scsw.ctrl & SCSW_ACTL_CH_ACTIVE) { in print_irb_err()
220 if (irb->scsw.ctrl & SCSW_ACTL_SUSPENDED) { in print_irb_err()
227 if (irb->scsw.ctrl & SCSW_SCTL_ALERT) { in print_irb_err()
230 if (irb->scsw.ctrl & SCSW_SCTL_INTERMED) { in print_irb_err()
233 if (irb->scsw.ctrl & SCSW_SCTL_PRIMARY) { in print_irb_err()
[all …]
/qemu/hw/s390x/
A Dcss.c84 VMSTATE_UINT16(ctrl, SCSW),
641 sch->curr_status.scsw.ctrl |= in css_conditional_io_interrupt()
1344 dest->ctrl = cpu_to_be16(src->ctrl); in copy_scsw_to_guest()
1420 dest->ctrl = be16_to_cpu(src->ctrl); in copy_scsw_from_guest()
1463 if (schib->scsw.ctrl & in css_do_msch()
1509 (!(schib->scsw.ctrl & in css_do_xsch()
1541 old_scsw_ctrl = schib->scsw.ctrl; in css_do_csch()
1550 schib->scsw.ctrl = old_scsw_ctrl; in css_do_csch()
1581 old_scsw_ctrl = schib->scsw.ctrl; in css_do_hsch()
1597 schib->scsw.ctrl = old_scsw_ctrl; in css_do_hsch()
[all …]
A D3270-ccw.c89 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in emulated_ccw_3270_cb()
90 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in emulated_ccw_3270_cb()
91 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | in emulated_ccw_3270_cb()
/qemu/hw/misc/
A Dmos6522.c69 int ctrl; in mos6522_set_irq() local
88 if ((positive_edge && (ctrl & C2_POS)) || in mos6522_set_irq()
95 if ((positive_edge && (ctrl & C1_POS)) || in mos6522_set_irq()
105 if ((positive_edge && (ctrl & C2_POS)) || in mos6522_set_irq()
112 if ((positive_edge && (ctrl & C1_POS)) || in mos6522_set_irq()
300 int ctrl; in mos6522_read() local
315 if (!(ctrl & C2_IND)) { in mos6522_read()
327 if (!(ctrl & C2_IND)) { in mos6522_read()
398 int ctrl; in mos6522_write() local
407 if (!(ctrl & C2_IND)) { in mos6522_write()
[all …]
A Darm_l2x0.c40 uint32_t ctrl; member
53 VMSTATE_UINT32(ctrl, L2x0State),
82 return s->ctrl; in l2x0_priv_read()
118 s->ctrl = value & 1; in l2x0_priv_write()
152 s->ctrl = 0; in l2x0_priv_reset()
A Dbcm2835_mphi.c52 val = s->ctrl; in mphi_reg_read()
88 s->ctrl = val; in mphi_reg_write()
133 s->ctrl = 0; in mphi_reset()
162 VMSTATE_UINT32(ctrl, BCM2835MphiState),
A Dtz-mpc.c133 if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) { in tz_mpc_autoinc_idx()
158 r = s->ctrl; in tz_mpc_reg_read()
257 oldval = s->ctrl; in tz_mpc_reg_write()
272 if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) && in tz_mpc_reg_write()
287 s->ctrl = value & (R_CTRL_SEC_RESP_MASK | in tz_mpc_reg_write()
385 return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK; in tz_mpc_handle_block()
476 s->ctrl = 0x00000100; in tz_mpc_reset()
578 VMSTATE_UINT32(ctrl, TZMPC),
/qemu/hw/dma/
A Dpl080.c46 VMSTATE_UINT32(ctrl, pl080_channel),
139 size = ch->ctrl & 0xfff; in pl080_run()
165 swidth = 1 << ((ch->ctrl >> 18) & 7); in pl080_run()
166 dwidth = 1 << ((ch->ctrl >> 21) & 7); in pl080_run()
170 if (ch->ctrl & PL080_CCTRL_SI) in pl080_run()
178 if (ch->ctrl & PL080_CCTRL_DI) in pl080_run()
183 ch->ctrl = (ch->ctrl & 0xfffff000) | size; in pl080_run()
206 if (ch->ctrl & PL080_CCTRL_I) { in pl080_run()
243 return s->chan[i].ctrl; in pl080_read()
307 s->chan[i].ctrl = value; in pl080_write()
[all …]
/qemu/hw/char/
A Dcmsdk-apb-uart.c106 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); in cmsdk_apb_uart_update()
120 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) { in uart_can_receive()
137 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { in uart_receive()
148 if (s->ctrl & R_CTRL_RX_INTEN_MASK) { in uart_receive()
170 r = s->ctrl; in uart_read()
201 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { in uart_transmit()
226 if (s->ctrl & R_CTRL_TX_INTEN_MASK) { in uart_transmit()
269 s->ctrl = value & 0x7f; in uart_write()
270 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) { in uart_write()
314 s->ctrl = 0; in cmsdk_apb_uart_reset()
[all …]
/qemu/hw/timer/
A Dcmsdk-apb-timer.c83 r = s->ctrl; in cmsdk_apb_timer_read()
123 s->ctrl = value & 0xf; in cmsdk_apb_timer_write()
125 if (s->ctrl & R_CTRL_EN_MASK) { in cmsdk_apb_timer_write()
139 if (value && (s->ctrl & R_CTRL_EN_MASK)) { in cmsdk_apb_timer_write()
154 if (value && (s->ctrl & R_CTRL_EN_MASK)) { in cmsdk_apb_timer_write()
187 if (s->ctrl & R_CTRL_IRQEN_MASK) { in cmsdk_apb_timer_tick()
198 s->ctrl = 0; in cmsdk_apb_timer_reset()
256 VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
A Daspeed_timer.c70 return !!(timer_to_ctrl(t)->ctrl & BIT(t->id * TIMER_CTRL_BITS + op)); in timer_ctrl_status()
250 value = s->ctrl; in aspeed_timer_read()
411 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; in aspeed_timer_set_ctrl()
426 s->ctrl = reg; in aspeed_timer_set_ctrl()
546 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); in aspeed_2500_timer_write()
586 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); in aspeed_2600_timer_write()
641 s->ctrl = 0; in aspeed_timer_reset()
666 VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
/qemu/target/microblaze/
A Dop_helper.c32 int test = ctrl & STREAM_TEST; in helper_put()
33 int atomic = ctrl & STREAM_ATOMIC; in helper_put()
34 int control = ctrl & STREAM_CONTROL; in helper_put()
35 int nonblock = ctrl & STREAM_NONBLOCK; in helper_put()
36 int exception = ctrl & STREAM_EXCEPTION; in helper_put()
47 uint32_t helper_get(uint32_t id, uint32_t ctrl) in helper_get() argument
49 int test = ctrl & STREAM_TEST; in helper_get()
50 int atomic = ctrl & STREAM_ATOMIC; in helper_get()
51 int control = ctrl & STREAM_CONTROL; in helper_get()
52 int nonblock = ctrl & STREAM_NONBLOCK; in helper_get()
[all …]
/qemu/tests/qtest/
A Daspeed_smc-test.c108 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); in spi_ctrl_setmode() local
109 ctrl &= ~(CTRL_USERMODE | 0xff << 16); in spi_ctrl_setmode()
110 ctrl |= mode | (cmd << 16); in spi_ctrl_setmode()
111 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_setmode()
116 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); in spi_ctrl_start_user() local
118 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; in spi_ctrl_start_user()
119 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_start_user()
121 ctrl &= ~CTRL_CE_STOP_ACTIVE; in spi_ctrl_start_user()
122 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_start_user()
129 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; in spi_ctrl_stop_user()
[all …]
/qemu/hw/vfio/
A Dccw.c332 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler()
333 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); in vfio_ccw_io_notifier_handler()
337 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler()
339 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler()
340 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | in vfio_ccw_io_notifier_handler()
345 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler()
347 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler()
348 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | in vfio_ccw_io_notifier_handler()
354 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler()
356 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler()
[all …]
/qemu/qapi/
A Dcommon.json188 # @ctrl-ctrl: left and right control key
198 # @ctrl-scrolllock: either control key and scroll lock key
203 'data': [ 'ctrl-ctrl', 'alt-alt', 'shift-shift','meta-meta', 'scrolllock',
204 'ctrl-scrolllock' ] }
/qemu/target/i386/
A Dops_sse.h1914 if (ctrl >> 8) { in pcmp_elen()
1919 if (ctrl & 1) { in pcmp_elen()
1934 if (ctrl & 1) { in pcmp_ilen()
1949 switch ((ctrl >> 0) & 3) { in pcmp_val()
1976 switch ((ctrl >> 2) & 3) { in pcmpxstrx()
2014 v &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i)); in pcmpxstrx()
2021 switch ((ctrl >> 4) & 3) { in pcmpxstrx()
2062 if ((ctrl >> 6) & 1) { in glue()
2063 if (ctrl & 1) { in glue()
2100 if ((ctrl >> 6) & 1) { in glue()
[all …]
/qemu/hw/ipack/
A Dtpci200.c68 uint8_t ctrl[N_MODULES]; member
120 if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) { in tpci200_set_irq()
139 if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) { in tpci200_set_irq()
153 if (dev->ctrl[i] & CTRL_INT_EDGE(j)) { in tpci200_set_irq()
217 ret = s->ctrl[ip_n]; in tpci200_read_las0()
259 s->ctrl[ip_n] = val; in tpci200_write_las0()
345 bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno); in tpci200_read_las1()
625 VMSTATE_UINT8_ARRAY(ctrl, TPCI200State, N_MODULES),
/qemu/include/hw/timer/
A Dnpcm7xx_timer.h61 NPCM7xxTimerCtrlState *ctrl; member
79 NPCM7xxTimerCtrlState *ctrl; member
/qemu/ui/
A Dsdl2-input.c48 bool ctrl = qkbd_state_modifier_get(scon->kbd, QKBD_MOD_CTRL); in sdl2_process_key() local
55 qemu_text_console_put_qcode(s, qcode, ctrl); in sdl2_process_key()
/qemu/include/hw/block/
A Dswim.h36 struct SWIMCtrl *ctrl; member
70 SWIMCtrl ctrl; member
/qemu/hw/cxl/
A Dcxl-host.c115 uint32_t ctrl, ig_enc, iw_enc, target_idx; in cxl_hdm_find_target() local
129 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc); in cxl_hdm_find_target()
130 if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) { in cxl_hdm_find_target()
134 ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG); in cxl_hdm_find_target()
135 iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW); in cxl_hdm_find_target()

Completed in 47 milliseconds

123456