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Searched refs:float_flag_divbyzero (Results 1 – 25 of 26) sorted by relevance

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/qemu/target/hexagon/
A Darch.c231 SOFTFLOAT_TEST_FLAG(float_flag_divbyzero, FPDBZF, FPDBZE); in arch_fpop_end()
278 float_raise(float_flag_divbyzero, fp_status); in arch_sf_recip_common()
/qemu/target/arm/
A Dvfp_helper.c44 if (host_bits & float_flag_divbyzero) { in vfp_exceptbits_from_host()
688 float_raise(float_flag_divbyzero, fpst); in HELPER()
738 float_raise(float_flag_divbyzero, fpst); in HELPER()
788 float_raise(float_flag_divbyzero, fpst); in HELPER()
887 float_raise(float_flag_divbyzero, s); in HELPER()
933 float_raise(float_flag_divbyzero, s); in HELPER()
978 float_raise(float_flag_divbyzero, s); in HELPER()
/qemu/include/fpu/
A Dsoftfloat-types.h149 float_flag_divbyzero = 0x0002, enumerator
/qemu/target/tricore/
A Dfpu_helper.c47 | float_flag_divbyzero in f_get_excp_flags()
107 if (flags & float_flag_divbyzero) { in f_update_psw_flags()
/qemu/target/openrisc/
A Dfpu_helper.c39 if (fexcp & float_flag_divbyzero) { in ieee_ex_to_openrisc()
/qemu/linux-user/arm/
A Dcpu_loop.c289 if (rc & float_flag_divbyzero) { in emulate_arm_fpa11()
/qemu/target/m68k/
A Dfpu_helper.c181 if (host_bits & float_flag_divbyzero) { in cpu_m68k_exceptbits_from_host()
205 host_bits |= float_flag_divbyzero; in cpu_m68k_exceptbits_to_host()
A Dsoftfloat.c257 float_raise(float_flag_divbyzero, status); in floatx80_lognp1()
454 float_raise(float_flag_divbyzero, status); in floatx80_logn()
619 float_raise(float_flag_divbyzero, status); in floatx80_log10()
678 float_raise(float_flag_divbyzero, status); in floatx80_log2()
2262 float_raise(float_flag_divbyzero, status); in floatx80_atanh()
/qemu/target/riscv/
A Dfpu_helper.c35 hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0; in riscv_cpu_get_fflags()
48 soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; in riscv_cpu_set_fflags()
A Dvector_helper.c3823 s->float_exception_flags |= float_flag_divbyzero; in frsqrt7_h()
3863 s->float_exception_flags |= float_flag_divbyzero; in frsqrt7_s()
3903 s->float_exception_flags |= float_flag_divbyzero; in frsqrt7_d()
4024 s->float_exception_flags |= float_flag_divbyzero; in frec7_h()
4056 s->float_exception_flags |= float_flag_divbyzero; in frec7_s()
4088 s->float_exception_flags |= float_flag_divbyzero; in frec7_d()
/qemu/target/rx/
A Dop_helper.c90 if (xcpt & float_flag_divbyzero) { in update_fpsw()
/qemu/target/alpha/
A Dfpu_helper.c50 ret |= CONVERT_BIT(exc, float_flag_divbyzero, FPCR_DZE); in soft_to_fpcr_exc()
/qemu/target/microblaze/
A Dop_helper.c125 if (flags & float_flag_divbyzero) { in update_fpu_flags()
/qemu/target/sh4/
A Dop_helper.c229 if (xcpt & float_flag_divbyzero) { in update_fpscr()
/qemu/target/hppa/
A Dfpu_helper.c85 hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK); in update_fr0_op()
/qemu/target/xtensa/
A Dfpu_helper.c56 { XTENSA_FP_Z, float_flag_divbyzero, },
/qemu/tests/fp/
A Dfp-test.c800 qemu_init_flags |= float_flag_divbyzero; in set_init_flags()
A Dwrap.c.inc48 if (qflags & float_flag_divbyzero) {
/qemu/target/sparc/
A Dfop_helper.c67 if (status & float_flag_divbyzero) { in check_ieee_exceptions()
/qemu/target/i386/tcg/
A Dfpu_helper.c191 (new_flags & float_flag_divbyzero ? FPUS_ZE : 0) | in merge_exception_flags()
2183 float_raise(float_flag_divbyzero, &env->fp_status); in helper_fyl2x()
3231 (mxcsr & FPUS_ZE ? float_flag_divbyzero : 0) | in update_mxcsr_status()
3255 (flags & float_flag_divbyzero ? FPUS_ZE : 0) | in update_mxcsr_from_sse_status()
/qemu/target/ppc/
A Dfpu_helper.c535 if (unlikely(flags & float_flag_divbyzero)) { in div_flags_handler()
743 if (unlikely(flags & float_flag_divbyzero)) { \ in FPU_FSQRT()
763 if (unlikely(flags & float_flag_divbyzero)) { \
1736 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1777 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { in helper_xsdivqp()
/qemu/target/loongarch/tcg/
A Dfpu_helper.c49 if (xcpt & float_flag_divbyzero) { in ieee_ex_to_loongarch()
/qemu/fpu/
A Dsoftfloat-parts.c.inc645 float_raise(float_flag_divbyzero, s);
1516 float_raise(float_flag_divbyzero, s);
/qemu/target/s390x/tcg/
A Dfpu_helper.c51 s390_exc |= (exc & float_flag_divbyzero) ? S390_IEEE_MASK_DIVBYZERO : 0; in s390_softfloat_exc_to_ieee()
/qemu/target/mips/tcg/
A Dfpu_helper.c193 if (ieee_xcpt & float_flag_divbyzero) { in ieee_to_mips_xcpt()

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