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Searched refs:iommu (Results 1 – 25 of 78) sorted by relevance

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/qemu/hw/remote/
A Diommu.c42 RemoteIommu *iommu = opaque; in remote_iommu_find_add_as() local
45 qemu_mutex_lock(&iommu->lock); in remote_iommu_find_add_as()
60 qemu_mutex_unlock(&iommu->lock); in remote_iommu_find_add_as()
85 RemoteIommu *iommu = REMOTE_IOMMU(obj); in remote_iommu_init() local
89 qemu_mutex_init(&iommu->lock); in remote_iommu_init()
94 RemoteIommu *iommu = REMOTE_IOMMU(obj); in remote_iommu_finalize() local
96 qemu_mutex_destroy(&iommu->lock); in remote_iommu_finalize()
98 g_hash_table_destroy(iommu->elem_by_devfn); in remote_iommu_finalize()
100 iommu->elem_by_devfn = NULL; in remote_iommu_finalize()
109 RemoteIommu *iommu = NULL; in remote_iommu_setup() local
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/qemu/docs/
A Dbypass-iommu.txt29 1. The following is the bypass iommu options:
34 (3) X86 default root bus bypass iommu:
57 -device intel-iommu \
60 - a default host bridge which bypass iommu
61 - a pxb host bridge which go through iommu
62 - a pxb host bridge which bypass iommu
68 iommu isolation. So it would be necessary to only bypass iommu for trusted
73 The bypass iommu feature includes:
75 Add bypass iommu property check of PCI Host and do not get iommu address
76 space for devices bypass iommu.
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/qemu/hw/riscv/
A Driscv-iommu-pci.c66 RISCVIOMMUState iommu; /* common IOMMU state */ member
72 RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); in riscv_iommu_pci_notify()
82 RISCVIOMMUState *iommu = &s->iommu; in riscv_iommu_pci_realize() local
93 DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", in riscv_iommu_pci_realize()
95 qdev_realize(DEVICE(iommu), NULL, errp); in riscv_iommu_pci_realize()
99 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); in riscv_iommu_pci_realize()
125 iommu->notify = riscv_iommu_pci_notify; in riscv_iommu_pci_realize()
136 riscv_iommu_pci_setup_iommu(iommu, bus, errp); in riscv_iommu_pci_realize()
152 RISCVIOMMUState *iommu = &s->iommu; in riscv_iommu_pci_init() local
155 qdev_alias_all_properties(DEVICE(iommu), obj); in riscv_iommu_pci_init()
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A Dmeson.build13 riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c'))
A Driscv-iommu.h56 void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
86 void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
/qemu/hw/s390x/
A Ds390-pci-bus.c561 if (addr < iommu->pba || addr > iommu->pal) { in s390_translate_iommu()
614 iommu = table->iommu[PCI_SLOT(devfn)]; in s390_pci_get_iommu()
615 if (!iommu) { in s390_pci_get_iommu()
626 memory_region_init(&iommu->mr, OBJECT(iommu), mr_name, UINT64_MAX); in s390_pci_get_iommu()
627 address_space_init(&iommu->as, &iommu->mr, as_name); in s390_pci_get_iommu()
630 table->iommu[PCI_SLOT(devfn)] = iommu; in s390_pci_get_iommu()
636 return iommu; in s390_pci_get_iommu()
644 return &iommu->as; in s390_pci_dma_iommu()
719 memory_region_init_iommu(&iommu->iommu_mr, sizeof(iommu->iommu_mr), in s390_pci_iommu_enable()
731 memory_region_del_subregion(&iommu->mr, MEMORY_REGION(&iommu->iommu_mr)); in s390_pci_iommu_disable()
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A Ds390-pci-inst.c30 if (iommu->dma_limit) { in inc_dma_avail()
37 if (iommu->dma_limit) { in dec_dma_avail()
666 return iommu->dma_limit ? iommu->dma_limit->avail : 1; in s390_pci_update_iotlb()
742 iommu = pbdev->iommu; in rpcit_service_call()
753 if (end < iommu->pba || start > iommu->pal) { in rpcit_service_call()
996 S390PCIIOMMU *iommu = pbdev->iommu; in reg_ioat() local
1017 iommu->pba = pba; in reg_ioat()
1018 iommu->pal = pal; in reg_ioat()
1029 iommu->pba = 0; in pci_dereg_ioat()
1030 iommu->pal = 0; in pci_dereg_ioat()
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/qemu/hw/ppc/
A Dspapr_iommu.c118 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); in spapr_tce_translate_iommu()
189 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); in spapr_tce_get_min_page_size()
194 static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu, in spapr_tce_get_attr() argument
197 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu); in spapr_tce_get_attr()
207 static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu, in spapr_tce_notify_flag_changed() argument
212 struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu); in spapr_tce_notify_flag_changed()
318 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu), in spapr_tce_table_realize()
401 memory_region_set_size(MEMORY_REGION(&tcet->iommu), in spapr_tce_table_enable()
404 MEMORY_REGION(&tcet->iommu)); in spapr_tce_table_enable()
414 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0); in spapr_tce_table_disable()
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/qemu/docs/specs/
A Driscv-iommu.rst1 .. _riscv-iommu:
9 The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
13 riscv-iommu-pci reference device
27 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci,[optional_pci_opts] (...)
52 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
61 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
64 Both will create iommu groups for the two e1000e cards.
68 use the riscv-iommu-pci device with the existing kernel support we need to emulate
74 -device riscv-iommu-pci,vendor-id=0x1efd,device-id=0xedf1 (...)
86 .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
/qemu/hw/i386/
A Dx86-iommu.c30 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu, in x86_iommu_iec_register_notifier() argument
38 QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list); in x86_iommu_iec_register_notifier()
41 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global, in x86_iommu_iec_notify_all() argument
48 QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) { in x86_iommu_iec_notify_all()
87 object_dynamic_cast(OBJECT(pcms->iommu), TYPE_X86_IOMMU_DEVICE)) { in x86_iommu_get_default()
88 return X86_IOMMU_DEVICE(pcms->iommu); in x86_iommu_get_default()
A Damd_iommu.c1035 AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); in amdvi_translate()
1089 static int amdvi_int_remap_legacy(AMDVIState *iommu, in amdvi_int_remap_legacy() argument
1148 static int amdvi_int_remap_ga(AMDVIState *iommu, in amdvi_int_remap_ga() argument
1183 if (iommu->xtsup) { in amdvi_int_remap_ga()
1193 static int __amdvi_int_remap_msi(AMDVIState *iommu, in __amdvi_int_remap_msi() argument
1220 if (iommu->ga_enabled) { in __amdvi_int_remap_msi()
1230 static int amdvi_int_remap_msi(AMDVIState *iommu, in amdvi_int_remap_msi() argument
1256 if (!iommu || !iommu->devtab_len) { in amdvi_int_remap_msi()
1261 if (!amdvi_get_dte(iommu, sid, dte)) { in amdvi_int_remap_msi()
1362 static int amdvi_int_remap(X86IOMMUState *iommu, in amdvi_int_remap() argument
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A Dintel_iommu.c1589 .private = (void *)&vtd_as->iommu, in vtd_sync_shadow_page_table_range()
3263 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); in vtd_iommu_translate()
3306 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); in vtd_iommu_notify_flag_changed()
3344 IntelIOMMUState *iommu = opaque; in vtd_post_load() local
3353 vtd_update_scalable_state(iommu); in vtd_post_load()
3355 vtd_update_iq_dw(iommu); in vtd_post_load()
3362 vtd_switch_address_space_all(iommu); in vtd_post_load()
3435 if (index >= iommu->intr_size) { in vtd_irte_get()
3555 if (!iommu->intr_eime) { in vtd_remap_irq_get()
3584 if (!iommu || !iommu->intr_enabled) { in vtd_interrupt_remap_msi()
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/qemu/hw/dma/
A Dsparc32_dma.c78 IOMMUState *is = (IOMMUState *)s->iommu; in ledma_memory_read()
99 IOMMUState *is = (IOMMUState *)s->iommu; in ledma_memory_write()
150 IOMMUState *is = (IOMMUState *)s->iommu; in espdma_memory_read()
161 IOMMUState *is = (IOMMUState *)s->iommu; in espdma_memory_write()
269 (Object **) &s->iommu, in sparc32_dma_device_init()
374 Object *iommu; in sparc32_dma_realize() local
376 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL); in sparc32_dma_realize()
377 if (!iommu) { in sparc32_dma_realize()
383 object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort); in sparc32_dma_realize()
397 object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort); in sparc32_dma_realize()
/qemu/tests/qtest/libqos/
A Dvirtio-iommu.c65 return qvirtio_iommu_get_driver(&v_iommu->iommu, interface); in qvirtio_iommu_pci_get_driver()
71 QVirtioIOMMU *interface = &iommu_pci->iommu; in qvirtio_iommu_pci_destructor()
81 QVirtioIOMMU *interface = &iommu_pci->iommu; in qvirtio_iommu_pci_start_hw()
93 QVirtioIOMMU *interface = &virtio_rpci->iommu; in virtio_iommu_pci_create()
A Dvirtio-iommu.h32 QVirtioIOMMU iommu; member
37 QVirtioIOMMU iommu; member
/qemu/hw/sparc64/
A Dsun4u_iommu.c75 static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, in sun4u_translate_iommu() argument
79 IOMMUState *is = container_of(iommu, IOMMUState, iommu); in sun4u_translate_iommu()
298 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), in iommu_init()
301 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); in iommu_init()
/qemu/hw/virtio/
A Dvhost-vdpa.c206 hwaddr iova = iotlb->iova + iommu->iommu_offset; in vhost_vdpa_iommu_map_notify()
207 VhostVDPAShared *s = iommu->dev_shared; in vhost_vdpa_iommu_map_notify()
259 struct vdpa_iommu *iommu; in vhost_vdpa_iommu_region_add() local
267 iommu = g_malloc0(sizeof(*iommu)); in vhost_vdpa_iommu_region_add()
273 iommu->iommu_mr = iommu_mr; in vhost_vdpa_iommu_region_add()
281 iommu->dev_shared = s; in vhost_vdpa_iommu_region_add()
285 g_free(iommu); in vhost_vdpa_iommu_region_add()
290 memory_region_iommu_replay(iommu->iommu_mr, &iommu->n); in vhost_vdpa_iommu_region_add()
300 struct vdpa_iommu *iommu; in vhost_vdpa_iommu_region_del() local
307 QLIST_REMOVE(iommu, iommu_next); in vhost_vdpa_iommu_region_del()
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A Dvhost.c865 struct vhost_dev *hdev = iommu->hdev; in vhost_iommu_unmap_notify()
879 struct vhost_iommu *iommu; in vhost_iommu_region_add() local
890 iommu = g_malloc0(sizeof(*iommu)); in vhost_iommu_region_add()
903 iommu->mr = section->mr; in vhost_iommu_region_add()
906 iommu->hdev = dev; in vhost_iommu_region_add()
918 struct vhost_iommu *iommu; in vhost_iommu_region_del() local
925 if (iommu->mr == section->mr && in vhost_iommu_region_del()
930 g_free(iommu); in vhost_iommu_region_del()
940 struct vhost_iommu *iommu; in vhost_toggle_device_iotlb() local
949 memory_region_unregister_iommu_notifier(iommu->mr, &iommu->n); in vhost_toggle_device_iotlb()
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/qemu/hw/sparc/
A Dsun4m_iommu.c287 static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, in sun4m_translate_iommu() argument
292 IOMMUState *is = container_of(iommu, IOMMUState, iommu); in sun4m_translate_iommu()
359 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), in iommu_init()
362 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); in iommu_init()
/qemu/include/hw/i386/
A Dx86-iommu.h40 int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
144 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
155 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
/qemu/tests/unit/
A Dtest-vmstate.c905 TestGTreeIOMMU *iommu = opaque; in iommu_preload() local
907 iommu->domains = g_tree_new_full((GCompareDataFunc)int_cmp, in iommu_preload()
1183 TestGTreeIOMMU *iommu = g_new0(TestGTreeIOMMU, 1); in create_iommu() local
1189 iommu->id = 7; in create_iommu()
1213 return iommu; in create_iommu()
1216 static void destroy_iommu(TestGTreeIOMMU *iommu) in destroy_iommu() argument
1218 g_tree_destroy(iommu->domains); in destroy_iommu()
1219 g_free(iommu); in destroy_iommu()
1224 TestGTreeIOMMU *iommu = create_iommu(); in test_gtree_save_iommu() local
1226 save_vmstate(&vmstate_iommu, iommu); in test_gtree_save_iommu()
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/qemu/docs/devel/
A Dvfio-iommufd.rst42 | /dev/iommu | /dev/vfio/vfio
57 | iommfd core | | device | | vfio iommu |
90 Interactions with the ``/dev/iommu`` are abstracted by a new iommufd
93 Any QEMU device (e.g. VFIO device) wishing to use ``/dev/iommu`` must
103 Note the ``/dev/iommu`` and VFIO cdev can be externally opened by a
/qemu/hw/alpha/
A Dtyphoon.c45 IOMMUMemoryRegion iommu; member
672 static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, in typhoon_translate_iommu() argument
677 TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu); in typhoon_translate_iommu()
899 memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu), in typhoon_init()
902 address_space_init(&s->pchip.iommu_as, MEMORY_REGION(&s->pchip.iommu), in typhoon_init()
/qemu/include/hw/s390x/
A Ds390-pci-bus.h291 S390PCIIOMMU *iommu[PCI_SLOT_MAX]; member
355 S390PCIIOMMU *iommu; member
391 void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
392 void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
/qemu/hw/arm/
A Dtrace-events18 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
56 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
57 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
58 …sid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid…

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