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Searched refs:irq (Results 1 – 25 of 689) sorted by relevance

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/qemu/hw/intc/
A Darm_gicv3_dist.c86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_ns_access()
107 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_bitmap_reg()
131 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_set_bitmap_reg()
155 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_clear_bitmap_reg()
179 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_bitmap_reg()
204 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_ipriorityr()
228 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_ipriorityr()
248 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_irouter()
270 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_irouter()
337 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writeb()
[all …]
A Dgic_internal.h29 #define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm)) argument
32 #define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm)) argument
34 #define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm)) argument
37 #define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true) argument
38 #define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false) argument
39 #define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model) argument
40 #define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm)) argument
41 #define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &= ~(cm)) argument
46 #define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger) argument
50 #define GIC_DIST_TARGET(irq) (s->irq_target[irq]) argument
[all …]
A Darm_gic.c88 int irq; in gic_get_best_irq() local
94 for (irq = 0; irq < s->num_irq; irq++) { in gic_get_best_irq()
95 if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && in gic_get_best_irq()
97 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { in gic_get_best_irq()
601 int ret, irq; in gic_acknowledge_irq() local
613 return irq; in gic_acknowledge_irq()
628 ret = irq; in gic_acknowledge_irq()
948 int irq; in gic_dist_readb() local
1195 int irq; in gic_dist_writeb() local
1418 if (irq >= GIC_INTERNAL && s->irq_state[irq].pending) { in gic_dist_writeb()
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A Daspeed_intc.c43 if (irq >= aic->num_ints) { in aspeed_intc_update()
45 __func__, irq); in aspeed_intc_update()
68 if (irq >= aic->num_ints) { in aspeed_intc_set_irq()
70 __func__, irq); in aspeed_intc_set_irq()
75 enable = s->enable[irq]; in aspeed_intc_set_irq()
104 s->pending[irq] |= select; in aspeed_intc_set_irq()
105 trace_aspeed_intc_pending_irq(irq, s->pending[irq]); in aspeed_intc_set_irq()
144 uint32_t irq; in aspeed_intc_write() local
167 if (irq >= aic->num_ints) { in aspeed_intc_write()
185 s->enable[irq] |= data; in aspeed_intc_write()
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A Driscv_aplic.c167 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_irq_rectified_val()
210 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_read_pending_word()
235 if ((irq <= 0) || (aplic->num_irqs <= irq)) { in riscv_aplic_set_pending()
271 uint32_t i, irq; in riscv_aplic_set_pending_word() local
275 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_set_pending_word()
292 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_read_enabled_word()
317 if ((irq <= 0) || (aplic->num_irqs <= irq)) { in riscv_aplic_set_enabled()
342 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_set_enabled_word()
448 for (irq = 1; irq < aplic->num_irqs; irq++) { in riscv_aplic_idc_topi()
528 assert((0 < irq) && (irq < aplic->num_irqs)); in riscv_aplic_request()
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A Darm_gic_kvm.c57 if (irq < (num_irq - GIC_INTERNAL)) { in kvm_arm_gic_set_irq()
64 irq += GIC_INTERNAL; in kvm_arm_gic_set_irq()
68 irq -= (num_irq - GIC_INTERNAL); in kvm_arm_gic_set_irq()
69 cpu = irq / GIC_INTERNAL; in kvm_arm_gic_set_irq()
70 irq %= GIC_INTERNAL; in kvm_arm_gic_set_irq()
140 GIC_DIST_SET_GROUP(irq, cm); in translate_group()
183 GIC_DIST_SET_ACTIVE(irq, cm); in translate_active()
238 int irq; in kvm_dist_get() local
244 irq = i * regsz; in kvm_dist_get()
266 int irq; in kvm_dist_put() local
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A Darm_gicv3.c49 if (irq <= cs->hppi.irq) { in irqbetter()
150 nmi = nmi & (1 << (irq & 0x1f)); in gicv3_get_priority()
167 *prio = cs->gicr_ipriorityr[irq]; in gicv3_get_priority()
201 cs->hppi.irq = i; in gicv3_redist_update_noirqset()
217 cs->hppi.irq = cs->hpplpi.irq; in gicv3_redist_update_noirqset()
237 (cs->hppi.irq < GIC_INTERNAL || in gicv3_redist_update_noirqset()
292 cs->hppi.irq = i; in gicv3_update_noirqset()
318 cs->hppi.irq >= start && cs->hppi.irq < start + len) { in gicv3_update_noirqset()
391 cpu = irq / GIC_INTERNAL; in gicv3_set_irq()
392 irq %= GIC_INTERNAL; in gicv3_set_irq()
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A Di8259.c109 int irq; in pic_update_irq() local
111 irq = pic_get_irq(s); in pic_update_irq()
112 if (irq >= 0) { in pic_update_irq()
124 int mask = 1 << irq; in pic_set_irq()
125 int irq_index = s->master ? irq : irq + 8; in pic_set_irq()
178 int irq, intno; in pic_read_irq() local
180 irq = pic_get_irq(s); in pic_read_irq()
181 if (irq >= 0) { in pic_read_irq()
184 if (irq == 2) { in pic_read_irq()
201 irq = 7; in pic_read_irq()
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A Darm_gicv3_redist.c34 assert(irq < 16); in gicr_ns_access()
120 ((prio == hpp->prio) && (irq <= hpp->irq))) { in update_for_one_lpi()
121 hpp->irq = irq; in update_for_one_lpi()
414 for (i = irq + 3; i >= irq; i--) { in gicr_readl()
568 for (i = irq; i < irq + 4; i++, value >>= 8) { in gicr_writel()
891 if (irq == cs->hpplpi.irq) { in gicv3_redist_lpi_pending()
959 if (irq == src->hpplpi.irq) { in gicv3_redist_mov_lpi()
1044 if (irq == cs->hppvlpi.irq) { in gicv3_redist_vlpi_pending()
1074 if (irq == cs->hppvlpi.irq) { in gicv3_redist_process_vlpi()
1099 if (vcpu_resident(src, src_vptaddr) && irq == src->hppvlpi.irq) { in gicv3_redist_mov_vlpi()
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A Dloongarch_extioi.c27 cpu = s->sw_coremap[irq]; in extioi_update_irq()
28 irq_index = irq / 32; in extioi_update_irq()
29 irq_mask = 1 << (irq & 0x1f); in extioi_update_irq()
60 set_bit32(irq, s->isr); in extioi_setirq()
113 int irq; in extioi_enable_irq() local
116 irq = ctz32(val); in extioi_enable_irq()
117 while (irq != 32) { in extioi_enable_irq()
123 val &= ~(1 << irq); in extioi_enable_irq()
124 irq = ctz32(val); in extioi_enable_irq()
237 while (irq != 32) { in extioi_writew()
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A Dxics.c95 irq->priority, irq->status); in ics_pic_print_info()
203 uint32_t irq; in icp_eoi() local
208 irq = xirr & XISR_MASK; in icp_eoi()
212 ics_eoi(ics, irq); in icp_eoi()
411 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); in ics_resend_msi()
424 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); in ics_resend_lsi()
439 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); in ics_set_irq_msi()
483 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); in ics_write_xive_msi()
496 irq->server = server; in ics_write_xive()
497 irq->priority = priority; in ics_write_xive()
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A Dxics_kvm.c196 ICSIRQState *irq = &ics->irqs[i]; in ics_get_kvm_state() local
217 irq->priority = 0xff; in ics_get_kvm_state()
219 irq->priority = irq->saved_priority; in ics_get_kvm_state()
222 irq->status = 0; in ics_get_kvm_state()
255 ICSIRQState *irq = &ics->irqs[srcno]; in ics_set_kvm_state_one() local
263 state = irq->server; in ics_set_kvm_state_one()
266 if (irq->priority != irq->saved_priority) { in ics_set_kvm_state_one()
267 assert(irq->priority == 0xff); in ics_set_kvm_state_one()
270 if (irq->priority == 0xff) { in ics_set_kvm_state_one()
274 if (irq->flags & XICS_FLAGS_IRQ_LSI) { in ics_set_kvm_state_one()
[all …]
A Dimx_avic.c71 qemu_set_irq(s->irq, !!flags); in imx_avic_update()
87 qemu_set_irq(s->irq, 0); in imx_avic_update()
96 irq, imx_avic_prio(s, irq)); in imx_avic_set_irq()
97 s->pending |= (1ULL << irq); in imx_avic_set_irq()
100 irq, imx_avic_prio(s, irq)); in imx_avic_set_irq()
101 s->pending &= ~(1ULL << irq); in imx_avic_set_irq()
159 int irq = -1; in imx_avic_read() local
164 irq = i; in imx_avic_read()
169 if (irq >= 0) { in imx_avic_read()
171 return irq << 16 | prio; in imx_avic_read()
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A Dgicv3_internal.h668 void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq);
712 int irq, int doorbell);
799 if (irq < GIC_INTERNAL) { in gicv3_irq_group()
800 grpbit = extract32(cs->gicr_igroupr0, irq, 1); in gicv3_irq_group()
803 grpbit = gicv3_gicd_group_test(s, irq); in gicv3_irq_group()
804 grpmodbit = gicv3_gicd_grpmod_test(s, irq); in gicv3_irq_group()
836 extract64(s->gicd_irouter[irq], 32, 8) << 24; in gicv3_cache_target_cpustate()
845 s->gicd_irouter_target[irq] = cs; in gicv3_cache_target_cpustate()
856 int irq; in gicv3_cache_all_target_cpustates() local
858 for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) { in gicv3_cache_all_target_cpustates()
[all …]
A Dloongson_liointc.c64 uint32_t irq, core, ip; in update_irq() local
79 for (irq = 0; irq < NUM_IRQS; irq++) { in update_irq()
80 if (!(p->isr & (1 << irq))) { in update_irq()
85 if ((p->mapper[irq] & (1 << core))) { in update_irq()
86 p->per_core_isr[core] |= (1 << irq); in update_irq()
91 if ((p->mapper[irq] & (1 << (ip + 4)))) { in update_irq()
92 per_ip_isr[ip] |= (1 << irq); in update_irq()
212 static void irq_handler(void *opaque, int irq, int level) in irq_handler() argument
216 p->pin_state &= ~(1 << irq); in irq_handler()
217 p->pin_state |= level << irq; in irq_handler()
A Darmv7m_nvic.c110 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase()
130 int irq; in nvic_isrpending() local
141 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { in nvic_isrpending()
509 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending()
548 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending()
560 assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV); in do_armv7m_nvic_set_pending()
595 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { in do_armv7m_nvic_set_pending()
694 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp()
701 switch (irq) { in armv7m_nvic_set_pending_lazyfp()
831 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq()
[all …]
/qemu/hw/core/
A Dirq.c31 if (!irq) in qemu_set_irq()
34 irq->handler(irq->opaque, irq->n, level); in qemu_set_irq()
40 irq->handler = handler; in init_irq_fields()
41 irq->opaque = opaque; in init_irq_fields()
42 irq->n = n; in init_irq_fields()
48 object_initialize(irq, sizeof(*irq), TYPE_IRQ); in qemu_init_irq()
77 return irq; in qemu_allocate_irq()
91 object_unref(OBJECT(irq)); in qemu_free_irq()
96 IRQState *irq = opaque; in qemu_notirq() local
98 irq->handler(irq->opaque, irq->n, !level); in qemu_notirq()
[all …]
/qemu/hw/mips/
A Dmips_int.c29 static void cpu_mips_irq_request(void *opaque, int irq, int level) in cpu_mips_irq_request() argument
35 if (irq < 0 || irq > 7) { in cpu_mips_irq_request()
42 env->CP0_Cause |= 1 << (irq + CP0Ca_IP); in cpu_mips_irq_request()
44 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); in cpu_mips_irq_request()
47 if (kvm_enabled() && (irq == 2 || irq == 3)) { in cpu_mips_irq_request()
48 kvm_mips_set_interrupt(cpu, irq, level); in cpu_mips_irq_request()
66 env->irq[i] = qi[i]; in cpu_mips_irq_init_cpu()
71 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) in cpu_mips_soft_irq() argument
73 if (irq < 0 || irq > 2) { in cpu_mips_soft_irq()
77 qemu_set_irq(env->irq[irq], level); in cpu_mips_soft_irq()
/qemu/include/hw/
A Dirq.h19 void qemu_set_irq(qemu_irq irq, int level);
21 static inline void qemu_irq_raise(qemu_irq irq) in qemu_irq_raise() argument
23 qemu_set_irq(irq, 1); in qemu_irq_raise()
26 static inline void qemu_irq_lower(qemu_irq irq) in qemu_irq_lower() argument
28 qemu_set_irq(irq, 0); in qemu_irq_lower()
31 static inline void qemu_irq_pulse(qemu_irq irq) in qemu_irq_pulse() argument
33 qemu_set_irq(irq, 1); in qemu_irq_pulse()
34 qemu_set_irq(irq, 0); in qemu_irq_pulse()
62 void qemu_free_irq(qemu_irq irq);
65 qemu_irq qemu_irq_invert(qemu_irq irq);
[all …]
/qemu/hw/m68k/
A Dq800-glue.c78 switch (irq) { in GLUE_set_irq()
80 irq = 0; in GLUE_set_irq()
84 irq = 1; in GLUE_set_irq()
93 irq = 3; in GLUE_set_irq()
97 irq = 6; in GLUE_set_irq()
112 irq = 5; in GLUE_set_irq()
116 irq = 1; in GLUE_set_irq()
120 irq = 2; in GLUE_set_irq()
124 irq = 3; in GLUE_set_irq()
128 irq = 6; in GLUE_set_irq()
[all …]
/qemu/hw/ppc/
A Dspapr_irq.c48 int irq; in spapr_irq_msi_alloc() local
60 if (irq == spapr->irq_map_nr) { in spapr_irq_msi_alloc()
67 return irq + SPAPR_IRQ_MSI; in spapr_irq_msi_alloc()
177 if (!spapr->irq->xics) { in spapr_irq_check()
312 if (spapr->irq->xics) { in spapr_irq_init()
328 if (spapr->irq->xive) { in spapr_irq_init()
379 assert(irq >= SPAPR_XIRQ_BASE); in spapr_irq_claim()
402 assert(irq >= SPAPR_XIRQ_BASE); in spapr_irq_free()
405 for (i = irq; i < (irq + num); i++) { in spapr_irq_free()
429 assert(irq >= SPAPR_XIRQ_BASE); in spapr_qirq()
[all …]
/qemu/hw/misc/
A Dstm32l4x5_exti.c59 static unsigned regbank_index_by_irq(unsigned irq) in regbank_index_by_irq() argument
61 return irq >= EXTI_MAX_IRQ_PER_BANK ? 1 : 0; in regbank_index_by_irq()
97 const unsigned bank = regbank_index_by_irq(irq); in stm32l4x5_exti_set_irq()
98 const int oirq = irq; in stm32l4x5_exti_set_irq()
100 trace_stm32l4x5_exti_set_irq(irq, level); in stm32l4x5_exti_set_irq()
103 irq %= EXTI_MAX_IRQ_PER_BANK; in stm32l4x5_exti_set_irq()
112 if (!extract32(s->imr[bank], irq, 1)) { in stm32l4x5_exti_set_irq()
117 if (extract32(exti_romask[bank], irq, 1)) { in stm32l4x5_exti_set_irq()
118 qemu_set_irq(s->irq[oirq], level); in stm32l4x5_exti_set_irq()
126 s->pr[bank] |= 1 << irq; in stm32l4x5_exti_set_irq()
[all …]
A Dstm32f4xx_exti.c44 static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) in stm32f4xx_exti_set_irq() argument
48 trace_stm32f4xx_exti_set_irq(irq, level); in stm32f4xx_exti_set_irq()
50 if (((1 << irq) & s->exti_rtsr) && level) { in stm32f4xx_exti_set_irq()
52 s->exti_pr |= 1 << irq; in stm32f4xx_exti_set_irq()
55 if (((1 << irq) & s->exti_ftsr) && !level) { in stm32f4xx_exti_set_irq()
57 s->exti_pr |= 1 << irq; in stm32f4xx_exti_set_irq()
60 if (!((1 << irq) & s->exti_imr)) { in stm32f4xx_exti_set_irq()
64 qemu_irq_pulse(s->irq[irq]); in stm32f4xx_exti_set_irq()
141 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); in stm32f4xx_exti_init()
/qemu/hw/arm/
A Dfsl-imx7.c169 qemu_irq irq; in fsl_imx7_realize() local
218 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); in fsl_imx7_realize()
219 sysbus_connect_irq(sbd, i, irq); in fsl_imx7_realize()
220 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); in fsl_imx7_realize()
221 sysbus_connect_irq(sbd, i + smp_cpus, irq); in fsl_imx7_realize()
222 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); in fsl_imx7_realize()
223 sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); in fsl_imx7_realize()
224 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); in fsl_imx7_realize()
225 sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); in fsl_imx7_realize()
601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); in fsl_imx7_realize()
[all …]
/qemu/hw/xtensa/
A Dmx_pic.c62 qemu_irq *irq; member
138 __func__, cpu, irq, changed_irq); in xtensa_mx_pic_update_cpu()
139 mx->cpu[cpu].irq_state_cache = irq; in xtensa_mx_pic_update_cpu()
145 qemu_set_irq(mx->cpu[cpu].irq[i], irq & mask); in xtensa_mx_pic_update_cpu()
276 qemu_irq *irq, in xtensa_mx_pic_register_cpu() argument
282 mx_cpu->irq = irq; in xtensa_mx_pic_register_cpu()
296 if (irq < mx->n_irq) { in xtensa_mx_pic_set_irq()
300 mx->ext_irq_state |= 1u << irq; in xtensa_mx_pic_set_irq()
302 mx->ext_irq_state &= ~(1u << irq); in xtensa_mx_pic_set_irq()
307 __func__, irq, active, in xtensa_mx_pic_set_irq()
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