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Searched refs:irq_state (Results 1 – 20 of 20) sorted by relevance

/qemu/hw/intc/
A Dgic_internal.h29 #define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
32 #define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm))
34 #define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm))
37 #define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true)
38 #define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false)
39 #define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model)
40 #define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm))
45 (s->irq_state[irq].edge_trigger = false)
52 #define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
169 return s->irq_state[irq].pending & cm; in gic_test_pending()
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A Dmips_gic.c33 gic->irq_state[i].map_vp == vp && in mips_gic_set_vp_irq()
34 gic->irq_state[i].enabled) { in mips_gic_set_vp_irq()
35 ored_level |= gic->irq_state[i].pending; in mips_gic_set_vp_irq()
60 int vp = gic->irq_state[n_IRQ].map_vp; in gic_update_pin_for_irq()
73 gic->irq_state[n_IRQ].pending = (uint8_t) level; in gic_set_irq()
74 if (!gic->irq_state[n_IRQ].enabled) { in gic_set_irq()
157 ret = gic->irq_state[irq_src].map_pin; in gic_read()
332 gic->irq_state[irq_src].map_vp = data; in gic_write()
376 gic->irq_state[i].enabled = 0; in gic_reset()
377 gic->irq_state[i].pending = 0; in gic_reset()
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A Darm_gic_common.c110 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
285 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); in arm_gic_common_reset_hold()
A Darm_gic_kvm.c419 memset(&s->irq_state[i], 0, sizeof(s->irq_state[0])); in kvm_arm_gic_get()
A Darm_gic.c1418 if (irq >= GIC_INTERNAL && s->irq_state[irq].pending) { in gic_dist_writeb()
1423 s->irq_state[irq].pending = value & ALL_CPU_MASK; in gic_dist_writeb()
/qemu/hw/pci/
A Dmsi.c325 uint32_t irq_state, vector_mask, pending; in msi_set_mask() local
335 irq_state = pci_get_long(dev->config + msi_mask_off(dev, msi64bit)); in msi_set_mask()
338 irq_state |= vector_mask; in msi_set_mask()
340 irq_state &= ~vector_mask; in msi_set_mask()
343 pci_set_long(dev->config + msi_mask_off(dev, msi64bit), irq_state); in msi_set_mask()
A Dpci.c305 return (d->irq_state >> irq_num) & 0x1; in pci_irq_state()
310 d->irq_state &= ~(0x1 << irq_num); in pci_set_irq_state()
311 d->irq_state |= level << irq_num; in pci_set_irq_state()
351 if (dev->irq_state) { in pci_update_irq_status()
411 assert(dev->irq_state == 0); in pci_do_device_reset()
707 uint32_t irq_state[PCI_NUM_PINS]; in get_pci_irq_state() local
710 irq_state[i] = qemu_get_be32(f); in get_pci_irq_state()
711 if (irq_state[i] != 0x1 && irq_state[i] != 0) { in get_pci_irq_state()
713 irq_state[i]); in get_pci_irq_state()
719 pci_set_irq_state(s, i, irq_state[i]); in get_pci_irq_state()
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/qemu/hw/ppc/
A Dpnv_occ.c54 bool irq_state; in pnv_occ_set_misc() local
59 irq_state = !!(val >> 63); in pnv_occ_set_misc()
60 qemu_set_irq(occ->psi_irq, irq_state); in pnv_occ_set_misc()
/qemu/hw/isa/
A Dvt82c686.c599 uint16_t irq_state[ISA_NUM_IRQS]; member
680 s->irq_state[0] |= mask; in via_isa_set_irq()
682 s->irq_state[0] &= ~mask; in via_isa_set_irq()
694 s->irq_state[irq] |= mask; in via_isa_set_irq()
696 s->irq_state[irq] &= ~mask; in via_isa_set_irq()
699 s->irq_state[irq] &= s->irq_state[0]; in via_isa_set_irq()
701 qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]); in via_isa_set_irq()
/qemu/include/hw/net/
A Dftgmac100.h44 uint32_t irq_state; member
/qemu/include/hw/intc/
A Darm_gic_common.h87 gic_irq_state irq_state[GIC_MAXIRQ]; member
A Dmips_gic.h206 MIPSGICIRQState *irq_state; member
/qemu/hw/net/
A Dmcf_fec.c41 uint32_t irq_state; member
200 changed = active ^s->irq_state; in mcf_fec_update()
208 s->irq_state = active; in mcf_fec_update()
A Dftgmac100.c1226 VMSTATE_UINT32(irq_state, FTGMAC100State),
/qemu/hw/mips/
A Dcps.c33 return s->gic.irq_state[pin_number].irq; in get_cps_irq()
/qemu/include/hw/pci/
A Dpci_device.h103 uint8_t irq_state; member
/qemu/hw/display/
A Dmacfb.c479 uint32_t irq_state = s->regs[DAFB_INTR_STAT >> 2] & in macfb_update_irq() local
482 if (irq_state) { in macfb_update_irq()
/qemu/target/arm/hvf/
A Dhvf.c1849 bool irq_state; in hvf_sync_vtimer() local
1859 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == in hvf_sync_vtimer()
1861 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); in hvf_sync_vtimer()
1863 if (!irq_state) { in hvf_sync_vtimer()
/qemu/target/s390x/kvm/
A Dkvm.c2056 struct kvm_s390_irq_state irq_state = { in kvm_s390_vcpu_interrupt_pre_save() local
2067 bytes = kvm_vcpu_ioctl(cs, KVM_S390_GET_IRQ_STATE, &irq_state); in kvm_s390_vcpu_interrupt_pre_save()
2080 struct kvm_s390_irq_state irq_state = { in kvm_s390_vcpu_interrupt_post_load() local
2094 r = kvm_vcpu_ioctl(cs, KVM_S390_SET_IRQ_STATE, &irq_state); in kvm_s390_vcpu_interrupt_post_load()
/qemu/hw/m68k/
A Dmcf5206.c30 int irq_state; member

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