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Searched refs:isr (Results 1 – 25 of 49) sorted by relevance

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/qemu/hw/char/
A Dstm32l4x5_usart.c160 s->isr |= R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
162 s->isr &= ~R_ISR_TEACK_MASK; in stm32l4x5_update_isr()
166 s->isr |= R_ISR_REACK_MASK; in stm32l4x5_update_isr()
168 s->isr &= ~R_ISR_REACK_MASK; in stm32l4x5_update_isr()
226 s->isr |= R_ISR_ORE_MASK; in stm32l4x5_usart_base_receive()
231 s->isr |= R_ISR_RXNE_MASK; in stm32l4x5_usart_base_receive()
385 s->isr = 0x020000C0; in stm32l4x5_usart_base_reset_hold()
398 s->isr &= ~R_ISR_RXNE_MASK; in usart_update_rqr()
436 retvalue = s->isr; in stm32l4x5_usart_base_read()
503 s->isr &= ~value; in stm32l4x5_usart_base_write()
[all …]
A Dipoctal232.c114 uint8_t isr; member
151 VMSTATE_UINT8(isr, SCC2698Block),
186 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { in update_irq()
212 blk->isr |= ISR_TXRDY(channel); in write_cr()
217 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
236 blk->isr &= ~ISR_RXRDY(channel); in write_cr()
241 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
271 uint8_t old_isr = blk->isr; in io_read()
309 ret = blk->isr; in io_read()
317 if (old_isr != blk->isr) { in io_read()
[all …]
A Dmcf_uart.c26 uint8_t isr; member
71 s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT); in OBJECT_DECLARE_SIMPLE_TYPE()
73 s->isr |= MCF_UART_TxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
76 s->isr |= MCF_UART_RxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
78 qemu_set_irq(s->irq, (s->isr & s->imr) != 0); in OBJECT_DECLARE_SIMPLE_TYPE()
113 return s->isr; in mcf_uart_read()
161 s->isr &= ~MCF_UART_DBINT; in mcf_do_command()
243 s->isr = 0; in mcf_uart_reset()
268 s->isr |= MCF_UART_DBINT; in mcf_uart_event()
/qemu/hw/gpio/
A Dimx_gpio.c72 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int()
73 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int()
75 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int()
91 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
98 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
104 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
184 reg_value = s->isr; in imx_gpio_read()
244 s->isr &= ~value; in imx_gpio_write()
286 VMSTATE_UINT32(isr, IMXGPIOState),
309 s->isr = 0; in imx_gpio_reset()
A Dzaurus.c49 uint16_t isr; member
99 return s->isr; in scoop_read()
143 s->isr = value; in scoop_write()
240 VMSTATE_UINT16(isr, ScoopInfo),
/qemu/hw/net/
A Dne2000.c128 s->isr = ENISR_RESET; in ne2000_reset()
142 int isr; in ne2000_update_irq() local
143 isr = (s->isr & s->imr) & 0x7f; in ne2000_update_irq()
146 isr ? 1 : 0, s->isr, s->imr); in ne2000_update_irq()
148 qemu_set_irq(s->irq, (isr != 0)); in ne2000_update_irq()
254 s->isr |= ENISR_RX; in ne2000_receive()
271 s->isr &= ~ENISR_RESET; in ne2000_ioport_write()
275 s->isr |= ENISR_RDC; in ne2000_ioport_write()
290 s->isr |= ENISR_TX; in ne2000_ioport_write()
383 ret = s->isr; in ne2000_ioport_read()
[all …]
A Dftgmac100.c269 qemu_set_irq(s->irq, s->isr & s->ier); in ftgmac100_update_irq()
510 s->isr |= FTGMAC100_INT_XPKT_LOST; in ftgmac100_insert_vlan()
518 s->isr |= FTGMAC100_INT_XPKT_LOST; in ftgmac100_insert_vlan()
585 s->isr |= FTGMAC100_INT_AHB_ERR; in ftgmac100_do_tx()
618 s->isr |= FTGMAC100_INT_XPKT_ETH; in ftgmac100_do_tx()
692 s->isr = 0; in ftgmac100_do_reset()
734 return s->isr; in ftgmac100_read()
791 s->isr &= ~value; in ftgmac100_write()
1075 s->isr |= FTGMAC100_INT_RPKT_FIFO; in ftgmac100_receive()
1088 s->isr |= FTGMAC100_INT_NO_RXBUF; in ftgmac100_receive()
[all …]
A Dmipsnet.c61 int isr = !!s->intctl; in mipsnet_update_irq() local
62 trace_mipsnet_irq(isr, s->intctl); in mipsnet_update_irq()
63 qemu_set_irq(s->irq, isr); in mipsnet_update_irq()
A Dpcnet.c717 int isr = 0; in pcnet_update_irq() local
740 isr = CSR_INEA(s); in pcnet_update_irq()
748 isr = 1; in pcnet_update_irq()
759 isr = 1; in pcnet_update_irq()
763 if (isr != s->isr) { in pcnet_update_irq()
764 trace_pcnet_isr_change(s, isr, s->isr); in pcnet_update_irq()
766 qemu_set_irq(s->irq, isr); in pcnet_update_irq()
767 s->isr = isr; in pcnet_update_irq()
1687 VMSTATE_INT32(isr, PCNetState),
/qemu/tests/qtest/
A Dbcm2835-dma-test.c53 int isr = readl(dma_base + BCM2708_DMA_INT_STATUS); in bcm2835_dma_test_interrupt() local
54 g_assert_cmpint(isr, ==, 0); in bcm2835_dma_test_interrupt()
86 isr = readl(RASPI3_DMA_BASE + BCM2708_DMA_INT_STATUS); in bcm2835_dma_test_interrupt()
87 g_assert_cmpint(isr, ==, 1 << dma_c); in bcm2835_dma_test_interrupt()
A Dstm32l4x5_usart-test.c307 uint32_t isr; in test_ack() local
319 isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); in test_ack()
320 g_assert_false(isr & R_ISR_TEACK_MASK); in test_ack()
321 g_assert_false(isr & R_ISR_REACK_MASK); in test_ack()
328 isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); in test_ack()
329 g_assert_true(isr & R_ISR_TEACK_MASK); in test_ack()
330 g_assert_true(isr & R_ISR_REACK_MASK); in test_ack()
/qemu/hw/timer/
A Dmss-timer.c62 bool isr, ier; in timer_update_irq() local
64 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); in timer_update_irq()
66 qemu_set_irq(st->irq, (ier && isr)); in timer_update_irq()
92 int isr; in timer_read() local
113 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); in timer_read()
115 ret = ier & isr; in timer_read()
A Dhpet.c84 uint64_t isr; /* interrupt status reg */ member
207 s->isr |= mask; in update_irq()
209 s->isr &= ~mask; in update_irq()
352 VMSTATE_UINT64(isr, HPETState),
431 if (s->isr & (1 << t->tn)) { in hpet_del_timer()
482 return s->isr >> shift; in hpet_ram_read()
527 && (s->isr & (1 << timer_id))) { in hpet_ram_write()
583 if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) { in hpet_ram_write()
609 cleared = new_val & s->isr; in hpet_ram_write()
/qemu/hw/intc/
A Dloongson_liointc.c53 uint32_t isr; member
68 p->isr = p->pin_state; in update_irq()
71 p->isr &= p->ien; in update_irq()
80 if (!(p->isr & (1 << irq))) { in update_irq()
140 r = p->isr; in liointc_read()
A Di8259.c90 mask = s->isr; in pic_get_irq()
167 s->isr |= (1 << irq); in pic_intack()
267 priority = get_priority(s, s->isr); in pic_ioport_write()
270 s->isr &= ~(1 << irq); in pic_ioport_write()
279 s->isr &= ~(1 << irq); in pic_ioport_write()
288 s->isr &= ~(1 << irq); in pic_ioport_write()
342 ret = s->isr; in pic_ioport_read()
A Dapic.c113 start = offsetof(VAPICState, isr); in apic_sync_vapic()
114 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); in apic_sync_vapic()
125 vector = get_highest_priority_int(s->isr); in apic_sync_vapic()
129 vapic_state.isr = vector & 0xf0; in apic_sync_vapic()
414 isrv = get_highest_priority_int(s->isr); in apic_get_ppr()
506 isrv = get_highest_priority_int(s->isr); in apic_eoi()
509 apic_reset_bit(s->isr, isrv); in apic_eoi()
749 apic_set_bit(s->isr, intno); in apic_get_interrupt()
851 val = s->isr[index & 7]; in apic_register_read()
A Dloongarch_extioi.c60 set_bit32(irq, s->isr); in extioi_setirq()
62 clear_bit32(irq, s->isr); in extioi_setirq()
115 val = mask & s->isr[index]; in extioi_enable_irq()
152 if (notify && test_bit32(irq + i, s->isr)) { in extioi_update_sw_coremap()
414 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
A Di8259_common.c41 s->isr = 0; in pic_reset_common()
141 s->master ? 0 : 1, s->irr, s->imr, s->isr, in pic_print_info()
175 VMSTATE_UINT8(isr, PICCommonState),
/qemu/hw/i386/kvm/
A Di8259.c55 s->isr = kpic->isr; in kvm_pic_get()
83 kpic->isr = s->isr; in kvm_pic_put()
/qemu/tests/qtest/libqos/
A Dvirtio-mmio.c95 uint32_t isr; in qvirtio_mmio_get_queue_isr_status() local
97 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1; in qvirtio_mmio_get_queue_isr_status()
98 if (isr != 0) { in qvirtio_mmio_get_queue_isr_status()
109 uint32_t isr; in qvirtio_mmio_get_config_isr_status() local
111 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2; in qvirtio_mmio_get_config_isr_status()
112 if (isr != 0) { in qvirtio_mmio_get_config_isr_status()
/qemu/hw/display/
A Dvirtio-vga.c151 vpci_dev->isr.size /= 2; in virtio_vga_base_realize()
159 offset -= vpci_dev->isr.size; in virtio_vga_base_realize()
160 vpci_dev->isr.offset = offset; in virtio_vga_base_realize()
/qemu/hw/net/can/
A Dtrace-events2 xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
12 xlnx_canfd_update_irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0…
/qemu/include/hw/i386/
A Dapic_internal.h171 uint32_t isr[8]; /* in service register */ member
197 uint8_t isr; member
/qemu/linux-user/hppa/
A Dtarget_syscall.h17 target_ulong isr; member
/qemu/include/hw/gpio/
A Dimx_gpio.h55 uint32_t isr; member

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