| /qemu/util/ |
| A D | hbitmap.c | 98 unsigned long *levels[HBITMAP_LEVELS]; member
117 cur = hbi->cur[i] & hb->levels[i][pos]; in hbitmap_iter_skip_words()
139 cur = hb->levels[i + 1][pos]; in hbitmap_iter_skip_words()
450 hb->levels[level][i] = ~0UL; in hb_set_between()
539 hb->levels[level][i] = 0UL; in hb_reset_between()
595 hb->levels[0][0] = 1UL << (BITS_PER_LONG - 1); in hbitmap_reset_all()
773 if (bitmap->levels[lev + 1][i]) { in hbitmap_deserialize_finish()
789 g_free(hb->levels[i]); in hbitmap_free()
865 hb->levels[i] = g_renew(unsigned long, hb->levels[i], size); in hbitmap_truncate()
867 memset(&hb->levels[i][old], 0x00, in hbitmap_truncate()
[all …]
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| /qemu/target/riscv/ |
| A D | monitor.c | 148 int levels, ptidxbits, ptesize, vm, va_bits; in mem_info_svxx() local
166 levels = 2; in mem_info_svxx()
171 levels = 3; in mem_info_svxx()
176 levels = 4; in mem_info_svxx()
181 levels = 5; in mem_info_svxx()
190 va_bits = PGSHIFT + levels * ptidxbits; in mem_info_svxx()
202 walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, in mem_info_svxx()
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| A D | cpu_helper.c | 924 int levels, ptidxbits, ptesize, vm, widened; in get_physical_address() local
958 levels = 2; ptidxbits = 10; ptesize = 4; break; in get_physical_address()
960 levels = 3; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
962 levels = 4; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
964 levels = 5; ptidxbits = 9; ptesize = 8; break; in get_physical_address()
974 int va_bits = PGSHIFT + levels * ptidxbits + widened; in get_physical_address()
1007 int ptshift = (levels - 1) * ptidxbits; in get_physical_address()
1015 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { in get_physical_address()
1265 if ((i != (levels - 1)) || (napot_bits != 4)) { in get_physical_address()
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| /qemu/hw/intc/ |
| A D | heathrow_pic.c | 35 return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask; in heathrow_check_irq()
98 value = pic->levels; in heathrow_read()
124 last_level = (pic->levels & irq_bit) ? 1 : 0; in heathrow_set_irq()
128 pic->levels |= irq_bit; in heathrow_set_irq()
130 pic->levels &= ~irq_bit; in heathrow_set_irq()
147 VMSTATE_UINT32(levels, HeathrowPICState),
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| A D | aspeed_intc.c | 82 if (s->orgates[irq].levels[i]) { in aspeed_intc_set_irq()
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| /qemu/hw/core/ |
| A D | or-irq.c | 38 s->levels[n] = level; in or_irq_handler()
41 or_level |= s->levels[i]; in or_irq_handler()
53 s->levels[i] = false; in or_irq_reset()
98 VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
109 VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
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| /qemu/scripts/ |
| A D | cpu-x86-uarch-abi.py | 20 levels = [ variable
128 for level in range(len(levels)):
130 want = set(levels[level])
147 for level in range(len(levels)):
185 for level in range(len(levels)):
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| /qemu/hw/vfio/ |
| A D | spapr.c | 295 create.levels = bits_total / bits_per_level; in vfio_spapr_create_window()
297 ++create.levels; in vfio_spapr_create_window()
300 for ( ; create.levels <= max_levels; ++create.levels) { in vfio_spapr_create_window()
320 create.levels, in vfio_spapr_create_window()
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| A D | trace-events | 140 vfio_spapr_create_window(int ps, unsigned int levels, uint64_t ws, uint64_t off) "pageshift=0x%x le…
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| /qemu/docs/specs/ |
| A D | ppc-spapr-numa.rst | 51 the NUMA levels for the platform.
67 three NUMA levels:
77 P2 processors, we would have the following NUMA levels:
150 the distance of the previous level, and the maximum amount of levels is
156 * resources two NUMA levels apart: 40
157 * resources three NUMA levels apart: 80
158 * resources four NUMA levels apart: 160
168 for 4 distinct NUMA distance values based on the NUMA levels
171 NUMA levels, granting user flexibility
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| /qemu/include/hw/ |
| A D | or-irq.h | 44 bool levels[MAX_OR_LINES]; member
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| /qemu/include/hw/intc/ |
| A D | heathrow_pic.h | 38 uint32_t levels; member
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| /qemu/hw/riscv/ |
| A D | riscv-iommu.c | 264 unsigned char levels; in riscv_iommu_spa_fetch() member
319 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
328 sc[pass].levels = 2; in riscv_iommu_spa_fetch()
339 sc[pass].levels = 0; in riscv_iommu_spa_fetch()
348 sc[pass].levels = 3; in riscv_iommu_spa_fetch()
357 sc[pass].levels = 4; in riscv_iommu_spa_fetch()
366 sc[pass].levels = 5; in riscv_iommu_spa_fetch()
387 (sc[pass].levels - 1 - sc[pass].step); in riscv_iommu_spa_fetch()
439 sc[pass].step = sc[pass].levels; in riscv_iommu_spa_fetch()
444 if (pass && sc[0].step != sc[0].levels) { in riscv_iommu_spa_fetch()
[all …]
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| /qemu/docs/system/ |
| A D | cpu-models-x86.rst.inc | 42 ABI compatibility levels for CPU models
45 The x86_64 architecture has a number of `ABI compatibility levels`_
49 table that follows illustrates which ABI compatibility levels
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
75 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
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| A D | qemu-block-drivers.rst.inc | 713 *debug* is the logging level of the gluster protocol driver. Debug levels
715 The default level is 4. The current logging levels defined in the gluster source
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| /qemu/linux-headers/linux/ |
| A D | vfio.h | 1691 __u32 levels; member
1803 __u32 levels; member
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| /qemu/qapi/ |
| A D | machine-common.json | 25 # An enumeration of CPU topology levels.
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| /qemu/hw/gpio/ |
| A D | trace-events | 43 …ins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
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| /qemu/docs/devel/migration/ |
| A D | qatzip-compression.rst | 118 comp_level value is 1, and it supports levels from 1 to 9
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| /qemu/ui/ |
| A D | vnc.h | 205 int levels[4]; member
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| A D | vnc-enc-tight.c | 806 vs->tight->levels[stream_id] = level; in tight_init_stream()
810 if (vs->tight->levels[stream_id] != level) { in tight_init_stream()
814 vs->tight->levels[stream_id] = level; in tight_init_stream()
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| /qemu/docs/system/arm/ |
| A D | emulation.rst | 25 - FEAT_BBM at level 2 (Translation table break-before-make levels)
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| /qemu/docs/system/s390x/ |
| A D | cpu-topology.rst | 6 Since QEMU 8.2, CPU topology on s390x provides up to 3 levels of
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| /qemu/target/arm/ |
| A D | ptw.c | 1548 int sl0, sl2, startlevel, granulebits, levels; in check_s2_mmu_setup() local
1627 levels = 3 - startlevel; in check_s2_mmu_setup()
1630 s1_min_iasize = levels * stride + granulebits + 1; in check_s2_mmu_setup()
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| /qemu/docs/system/i386/ |
| A D | hyperv.rst | 307 QAPI by higher levels of the virtualization stack. Enabling this feature
|