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Searched refs:limit (Results 1 – 25 of 164) sorted by relevance

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/qemu/include/qemu/
A Dratelimit.h45 QEMU_LOCK_GUARD(&limit->lock); in ratelimit_calculate_delay()
46 if (!limit->slice_quota) { in ratelimit_calculate_delay()
50 assert(limit->slice_ns); in ratelimit_calculate_delay()
56 limit->slice_end_time = now + limit->slice_ns; in ratelimit_calculate_delay()
57 limit->dispatched = 0; in ratelimit_calculate_delay()
60 limit->dispatched += n; in ratelimit_calculate_delay()
61 if (limit->dispatched < limit->slice_quota) { in ratelimit_calculate_delay()
69 delay_slices = (double)limit->dispatched / limit->slice_quota; in ratelimit_calculate_delay()
70 limit->slice_end_time = limit->slice_start_time + in ratelimit_calculate_delay()
89 limit->slice_ns = slice_ns; in ratelimit_set_speed()
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/qemu/hw/timer/
A Dslavio_timer.c59 uint64_t limit; member
109 uint64_t count, limit; in slavio_timer_get_out() local
112 limit = TIMER_MAX_COUNT32; in slavio_timer_get_out()
114 limit = t->limit; in slavio_timer_get_out()
133 if (t->limit != 0) { in slavio_timer_irq()
220 t->limit = TIMER_MAX_COUNT64; in slavio_timer_mem_writel()
244 t->limit = TIMER_MAX_COUNT64; in slavio_timer_mem_writel()
258 t->limit = val & TIMER_MAX_COUNT32; in slavio_timer_mem_writel()
260 if (t->limit == 0) { /* free-run */ in slavio_timer_mem_writel()
348 VMSTATE_UINT64(limit, CPUTimerState),
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A Darm_timer.c35 uint32_t limit; member
60 return s->limit; in arm_timer_read()
84 uint32_t limit; in arm_timer_recalibrate() local
89 limit = 0xffffffff; in arm_timer_recalibrate()
91 limit = 0xffff; in arm_timer_recalibrate()
94 limit = s->limit; in arm_timer_recalibrate()
96 ptimer_set_limit(s->timer, limit, reload); in arm_timer_recalibrate()
107 s->limit = value; in arm_timer_write()
143 s->limit = value; in arm_timer_write()
168 VMSTATE_UINT32(limit, arm_timer_state),
A Dimx_epit.c176 uint64_t limit = ptimer_get_limit(s->timer_cmp); in imx_epit_update_compare_timer() local
182 is_oneshot = (limit < s->cmp); in imx_epit_update_compare_timer()
194 counter += limit - s->cmp; in imx_epit_update_compare_timer()
254 uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; in imx_epit_write_cr() local
255 ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); in imx_epit_write_cr()
257 ptimer_set_limit(s->timer_cmp, limit, 0); in imx_epit_write_cr()
/qemu/target/i386/hvf/
A Dx86.c54 uint32_t limit; in x86_read_segment_descriptor() local
65 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_read_segment_descriptor()
68 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_read_segment_descriptor()
71 if (sel.index * 8 >= limit) { in x86_read_segment_descriptor()
84 uint32_t limit; in x86_write_segment_descriptor() local
88 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_write_segment_descriptor()
91 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_write_segment_descriptor()
94 if (sel.index * 8 >= limit) { in x86_write_segment_descriptor()
106 uint32_t limit = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); in x86_read_call_gate() local
109 if (gate * 8 >= limit) { in x86_read_call_gate()
A Dx86_descr.c28 .limit = VMCS_GUEST_##seg##_LIMIT, \
35 int limit; member
50 return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_limit()
79 desc->limit = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_descriptor()
88 wvmcs(cpu->accel->fd, sf->limit, desc->limit); in vmx_write_segment_descriptor()
99 vmx_desc->limit = x86_segment_limit(desc); in x86_segment_descriptor_to_vmx()
115 x86_set_segment_limit(desc, vmx_desc->limit); in vmx_segment_to_x86_descriptor()
A Dx86.h153 uint32_t limit = (uint32_t)((desc->limit1 << 16) | desc->limit0); in x86_segment_limit() local
155 return (limit << 12) | 0xfff; in x86_segment_limit()
157 return limit; in x86_segment_limit()
161 uint32_t limit) in x86_set_segment_limit() argument
163 desc->limit0 = limit & 0xffff; in x86_set_segment_limit()
164 desc->limit1 = limit >> 16; in x86_set_segment_limit()
/qemu/hw/core/
A Dptimer.c25 uint64_t limit; member
83 delta = s->delta = s->limit; in ptimer_reload()
102 if (s->enabled == 1 && s->limit == 0) { in ptimer_reload()
114 if (s->enabled == 1 && s->limit != 0) { in ptimer_reload()
175 if (s->delta == 0 || s->limit == 0) { in ptimer_tick()
189 s->delta = s->limit; in ptimer_tick()
273 } else if (counter == s->limit) { in ptimer_get_count()
401 s->limit = limit; in ptimer_set_limit()
403 s->delta = limit; in ptimer_set_limit()
411 return s->limit; in ptimer_get_limit()
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/qemu/docs/devel/migration/
A Ddirty-limit.rst1 Dirty limit
4 The dirty limit, short for dirty page rate upper limit, is a new capability
36 page rate value and the corresponding upper limit of the VM:
40 limit is specified by caller, therefore fetch it directly.
47 rate progressively down to the upper limit without oscillation. To
50 to the limit, which is used when the current dirty page rate is far
51 from the limit; the second is to add or subtract a fixed time when
52 the current dirty page rate is close to the limit.
60 to step PREPARE (1) until the dirty limit is reached.
68 In summary, thanks to the KVM dirty ring technology, the dirty limit
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/qemu/hw/pci/
A Dpci_host.c57 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) in pci_adjust_config_limit() argument
59 if ((*limit > PCI_CONFIG_SPACE_SIZE) && in pci_adjust_config_limit()
61 *limit = PCI_CONFIG_SPACE_SIZE; in pci_adjust_config_limit()
77 uint32_t limit, uint32_t val, uint32_t len) in pci_host_config_write_common() argument
79 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); in pci_host_config_write_common()
80 if (limit <= addr) { in pci_host_config_write_common()
96 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); in pci_host_config_write_common()
100 uint32_t limit, uint32_t len) in pci_host_config_read_common() argument
104 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); in pci_host_config_read_common()
105 if (limit <= addr) { in pci_host_config_read_common()
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A Dpcie_host.c42 uint32_t limit; in pcie_mmcfg_data_write() local
48 limit = pci_config_size(pci_dev); in pcie_mmcfg_data_write()
49 pci_host_config_write_common(pci_dev, addr, limit, val, len); in pcie_mmcfg_data_write()
60 uint32_t limit; in pcie_mmcfg_data_read() local
66 limit = pci_config_size(pci_dev); in pcie_mmcfg_data_read()
67 return pci_host_config_read_common(pci_dev, addr, limit, len); in pcie_mmcfg_data_read()
A Dpci_bridge.c131 pcibus_t limit; in pci_bridge_get_limit() local
133 limit = pci_config_get_io_base(bridge, in pci_bridge_get_limit()
135 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ in pci_bridge_get_limit()
138 limit = pci_config_get_pref_base( in pci_bridge_get_limit()
141 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); in pci_bridge_get_limit()
143 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ in pci_bridge_get_limit()
145 return limit; in pci_bridge_get_limit()
156 pcibus_t limit = pci_bridge_get_limit(bridge_dev, type); in pci_bridge_init_alias() local
159 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; in pci_bridge_init_alias()
/qemu/hw/sensor/
A Dtmp105.c57 if (s->temperature < s->limit[0]) { in tmp105_alarm_update()
62 if (s->temperature >= s->limit[1]) { in tmp105_alarm_update()
74 if (s->temperature < s->limit[0]) { in tmp105_alarm_update()
79 if (s->temperature >= s->limit[1]) { in tmp105_alarm_update()
145 s->buf[s->len++] = ((uint16_t) s->limit[0]) >> 8; in tmp105_read()
146 s->buf[s->len++] = ((uint16_t) s->limit[0]) >> 0; in tmp105_read()
150 s->buf[s->len++] = ((uint16_t) s->limit[1]) >> 8; in tmp105_read()
178 s->limit[s->pointer & 1] = (int16_t) in tmp105_write()
271 VMSTATE_INT16_ARRAY(limit, TMP105State, 2),
293 s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ in tmp105_reset()
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/qemu/target/i386/tcg/sysemu/
A Dsmm_helper.c62 x86_stl_phys(cs, sm_state + offset + 4, dt->limit); in do_smm_enter()
67 x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit); in do_smm_enter()
71 x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit); in do_smm_enter()
75 x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit); in do_smm_enter()
79 x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit); in do_smm_enter()
128 x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit); in do_smm_enter()
133 x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit); in do_smm_enter()
137 x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit); in do_smm_enter()
140 x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit); in do_smm_enter()
219 env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94); in helper_rsm()
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A Dsvm_helper.c37 cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
38 sc->limit, mmu_idx, 0); in svm_save_seg()
66 sc->limit = in svm_load_seg()
67 cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_load_seg()
84 sc.base, sc.limit, sc.flags); in svm_load_seg_cache()
189 x86_stl_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit), in helper_vmrun()
190 env->gdt.limit); in helper_vmrun()
194 x86_stl_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit), in helper_vmrun()
195 env->idt.limit); in helper_vmrun()
785 env->gdt.limit); in do_vmexit()
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/qemu/bsd-user/i386/
A Dtarget_arch_cpu.c35 void bsd_i386_write_dt(void *ptr, unsigned long addr, unsigned long limit, in bsd_i386_write_dt() argument
40 e1 = (addr << 16) | (limit & 0xffff); in bsd_i386_write_dt()
41 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); in bsd_i386_write_dt()
/qemu/hw/sparc64/
A Dtrace-events22 … char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit=0x%"PRIx64 " (%s…
23 sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=ZERO - not starting timer"
/qemu/bsd-user/x86_64/
A Dtarget_arch_cpu.c36 unsigned long limit, int flags) in bsd_x86_64_write_dt() argument
40 e1 = (addr << 16) | (limit & 0xffff); in bsd_x86_64_write_dt()
41 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); in bsd_x86_64_write_dt()
/qemu/target/i386/tcg/
A Dseg_helper.c146 if ((index + 7) > dt->limit) { in load_segment_ra()
163 unsigned int limit; in get_seg_limit() local
167 limit = (limit << 12) | 0xfff; in get_seg_limit()
169 return limit; in get_seg_limit()
500 env->tr.limit = tss_limit; in switch_tss_ra()
536 env->ldt.limit = 0; in switch_tss_ra()
1259 env->ldt.limit = 0; in helper_lldt()
1313 env->tr.limit = 0; in helper_ltr()
1491 if (new_eip > limit && in helper_ljmp_protected()
2328 unsigned int limit; in helper_lsl() local
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/qemu/accel/tcg/
A Dtcg-accel-ops-icount.c95 int64_t limit = icount_get_limit(); in icount_percpu_budget() local
96 int64_t timeslice = limit / cpu_count; in icount_percpu_budget()
99 timeslice = limit; in icount_percpu_budget()
/qemu/linux-user/i386/
A Dcpu_loop.c36 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, in write_dt() argument
41 e1 = (addr << 16) | (limit & 0xffff); in write_dt()
42 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); in write_dt()
389 env->idt.limit = 511; in target_cpu_copy_regs()
391 env->idt.limit = 255; in target_cpu_copy_regs()
393 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), in target_cpu_copy_regs()
410 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; in target_cpu_copy_regs()
/qemu/semihosting/
A Darm-compat-semi.c668 target_ulong limit; in do_common_semihosting() local
684 limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; in do_common_semihosting()
687 ret = do_brk(limit); in do_common_semihosting()
688 if (ret >= limit) { in do_common_semihosting()
691 limit = (ts->heap_base >> 1) + (limit >> 1); in do_common_semihosting()
693 ts->heap_limit = limit; in do_common_semihosting()
/qemu/hw/pci-host/
A Dgpex-acpi.c237 entry->base, entry->limit, in acpi_dsdt_add_gpex()
238 0x0000, entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
250 entry->limit, cfg->pio.base, in acpi_dsdt_add_gpex()
251 entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
264 entry->limit, 0x0000, in acpi_dsdt_add_gpex()
265 entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
/qemu/migration/
A Dmigration-stats.c49 void migration_rate_set(uint64_t limit) in migration_rate_set() argument
54 stat64_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO); in migration_rate_set()
/qemu/qapi/
A Dmigration.json833 # @vcpu-dirty-limit: Dirtyrate limit (MB/s) during live migration.
870 'vcpu-dirty-limit',
1014 # @vcpu-dirty-limit: Dirtyrate limit (MB/s) during live migration.
1224 # @vcpu-dirty-limit: Dirtyrate limit (MB/s) during live migration.
2189 # @limit-rate: upper limit of dirty page rate (MB/s) for a virtual
2198 'limit-rate': 'uint64',
2202 # @set-vcpu-dirty-limit:
2223 { 'command': 'set-vcpu-dirty-limit',
2228 # @cancel-vcpu-dirty-limit:
2250 # @query-vcpu-dirty-limit:
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