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Searched refs:master (Results 1 – 25 of 60) sorted by relevance

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/qemu/io/
A Dchannel-tls.c65 qio_channel_tls_new_server(QIOChannel *master, in qio_channel_tls_new_server() argument
76 tioc->master = master; in qio_channel_tls_new_server()
81 object_ref(OBJECT(master)); in qio_channel_tls_new_server()
108 qio_channel_tls_new_client(QIOChannel *master, in qio_channel_tls_new_client() argument
119 tioc->master = master; in qio_channel_tls_new_client()
124 object_ref(OBJECT(master)); in qio_channel_tls_new_client()
204 qio_channel_add_watch_full(ioc->master, in qio_channel_tls_handshake_task()
260 object_unref(OBJECT(ioc->master)); in qio_channel_tls_finalize()
350 qio_channel_set_delay(tioc->master, enabled); in qio_channel_tls_set_delay()
358 qio_channel_set_cork(tioc->master, enabled); in qio_channel_tls_set_cork()
[all …]
A Dchannel-websock.c493 ret = qio_channel_read(ioc->master, in qio_channel_websock_handshake_read()
539 ret = qio_channel_write(wioc->master, in qio_channel_websock_handshake_send()
601 wioc->master, in qio_channel_websock_handshake_io()
885 wioc->master = master; in qio_channel_websock_new_server()
890 object_ref(OBJECT(master)); in qio_channel_websock_new_server()
910 qio_channel_add_watch(ioc->master, in qio_channel_websock_handshake()
925 object_unref(OBJECT(ioc->master)); in qio_channel_websock_finalize()
944 ret = qio_channel_read(ioc->master, in qio_channel_websock_read_wire()
983 ret = qio_channel_write(ioc->master, in qio_channel_websock_write_wire()
1071 qio_channel_add_watch(ioc->master, in qio_channel_websock_set_watch()
[all …]
A Dtrace-events40 …channel_tls_new_client(void *ioc, void *master, void *creds, const char *hostname) "TLS new client…
41 …_channel_tls_new_server(void *ioc, void *master, void *creds, const char *aclname) "TLS new client…
51 qio_channel_websock_new_server(void *ioc, void *master) "Websock new client ioc=%p master=%p"
/qemu/
A D.gitpublish7 base = master
12 base = master
18 base = master
24 base = master
30 base = master
36 base = master
42 base = master
48 base = master
A DREADME.rst40 `<https://www.qemu.org/docs/master/>`_ is generated from the ``docs/``
42 <https://www.sphinx-doc.org/en/master/>`_.
81 <https://www.qemu.org/docs/master/devel/style.html>`_ of
113 $ git checkout master -b my-feature
/qemu/tests/unit/
A Dtest-crypto-secret.c392 Object *master = object_new_with_props( in test_secret_crypt_raw() local
418 object_unparent(master); in test_secret_crypt_raw()
425 Object *master = object_new_with_props( in test_secret_crypt_base64() local
450 object_unparent(master); in test_secret_crypt_base64()
457 Object *master = object_new_with_props( in test_secret_crypt_short_key() local
477 object_unparent(master); in test_secret_crypt_short_key()
483 Object *master = object_new_with_props( in test_secret_crypt_short_iv() local
503 object_unparent(master); in test_secret_crypt_short_iv()
509 Object *master = object_new_with_props( in test_secret_crypt_missing_iv() local
528 object_unparent(master); in test_secret_crypt_missing_iv()
[all …]
/qemu/hw/intc/
A Di8259_common.c92 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) in i8259_init_chip() argument
99 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0); in i8259_init_chip()
100 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1); in i8259_init_chip()
101 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde); in i8259_init_chip()
102 qdev_prop_set_bit(dev, "master", master); in i8259_init_chip()
123 if (s->master) { in pic_get_statistics()
141 s->master ? 0 : 1, s->irr, s->imr, s->isr, in pic_print_info()
200 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
A Di8259.c94 if (s->special_fully_nested_mode && s->master) { in pic_get_irq()
113 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); in pic_update_irq()
125 int irq_index = s->master ? irq : irq + 8; in pic_set_irq()
127 trace_pic_set_irq(s->master, irq, level); in pic_set_irq()
239 trace_pic_ioport_write(s->master, addr, val); in pic_ioport_write()
350 trace_pic_ioport_read(s->master, addr, ret); in pic_ioport_read()
A Dslavio_intctl.c54 struct SLAVIO_INTCTLState *master; member
121 slavio_check_interrupts(s->master, 1); in slavio_intctl_mem_writel()
127 slavio_check_interrupts(s->master, 1); in slavio_intctl_mem_writel()
440 s->slaves[i].master = s; in slavio_intctl_init()
/qemu/include/io/
A Dchannel-tls.h48 QIOChannel *master; member
79 qio_channel_tls_new_server(QIOChannel *master,
109 qio_channel_tls_new_client(QIOChannel *master,
A Dchannel-websock.h57 QIOChannel *master; member
88 qio_channel_websock_new_server(QIOChannel *master);
/qemu/docs/system/
A Dsecrets.rst113 A single master key can be used to encrypt all subsequent secrets, **but it is
136 and also encryption with a master key:
146 It is recommended for production deployments to use a master key secret, and
147 then pass all subsequent inline secrets encrypted with the master key.
149 Each QEMU instance must have a distinct master key, and that must be generated
150 from a cryptographically secure random data source. The master key should be
151 deleted immediately upon QEMU shutdown. If passing the master key as a file,
154 keyring can be used to pass the master key to QEMU.
157 with this master key.
162 The only item that needs strongly protecting is the master key file.
/qemu/docs/system/devices/
A Divshmem.rst41 With device property ``master=on``, the guest will copy the shared
42 memory on migration to the destination host. With ``master=off``, the
47 At most one of the devices sharing the same memory can be master. The
48 master must complete migration before you plug back the other devices.
/qemu/include/hw/isa/
A Di8259_internal.h66 uint32_t master; /* reflects /SP input pin */ member
74 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master);
/qemu/docs/system/riscv/
A Dshakti-c.rst11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
53 $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
71 $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
/qemu/docs/specs/
A Dfsi.rst6 master/slave and the end engine.
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
39 integration of the FSI master IP with the OPB, mainly the existence of an
89 dev: fsi.master, id ""
100 dev: fsi.master, id ""
/qemu/docs/devel/
A Dsubmitting-a-pull-request.rst61 **Pull requests not for master should say "not for master" and have
64 string "not for master" in the cover letter email, and make sure the
67 pull requests that should be applied to master.
/qemu/hw/ide/
A Dide-dev.c45 dev->unit = bus->master ? 1 : 0; in ide_qdev_realize()
56 if (bus->master) { in ide_qdev_realize()
60 bus->master = dev; in ide_qdev_realize()
/qemu/hw/misc/
A Divshmem.c118 OnOffAuto master; member
137 assert(s->master != ON_OFF_AUTO_AUTO); in ivshmem_is_master()
138 return s->master == ON_OFF_AUTO_ON; in ivshmem_is_master()
883 if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) { in ivshmem_common_realize()
898 if (s->master == ON_OFF_AUTO_AUTO) { in ivshmem_common_realize()
899 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; in ivshmem_common_realize()
1026 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1085 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
/qemu/hw/audio/
A Dwm8750.c57 int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master; member
245 if (s->master || !s->ext_dac_hz) in wm8750_clk_update()
250 if (s->master || !s->ext_adc_hz) in wm8750_clk_update()
255 if (s->master || (!s->ext_dac_hz && !s->ext_adc_hz)) { in wm8750_clk_update()
545 s->master = (value >> 6) & 1; /* MS */ in wm8750_tx()
546 wm8750_clk_update(s, s->master); in wm8750_tx()
/qemu/tests/qemu-iotests/
A D210.out54 master key iters: XXX
107 master key iters: XXX
163 master key iters: XXX
234 master key iters: XXX
A D198.out76 master key iters: 1024
122 master key iters: 1024
/qemu/tests/rocker/
A Dbridge12 simp ssh tut sw1 --cmd "sudo /sbin/ip link set dev sw1p1 master br0"
13 simp ssh tut sw1 --cmd "sudo /sbin/ip link set dev sw1p2 master br0"
A Dbridge-stp13 simp ssh tut sw1 --cmd "sudo /sbin/ip link set dev sw1p1 master br0"
14 simp ssh tut sw1 --cmd "sudo /sbin/ip link set dev sw1p2 master br0"
/qemu/hw/fsi/
A Dmeson.build1 system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))

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