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Searched refs:new_val (Results 1 – 23 of 23) sorted by relevance

/qemu/target/riscv/
A Dcsr.c2033 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); in rmw_iprio()
2174 val, new_val, wr_mask); in rmw_xtopei()
2596 val = (uint64_t)new_val << 32; in write_mstateenh()
2679 val = (uint64_t)new_val << 32; in write_hstateenh()
2760 env->software_seip = new_val & MIP_SEIP; in rmw_mip64()
2761 new_val |= env->external_seip * MIP_SEIP; in rmw_mip64()
3025 new_val &= ~(VS_MODE_INTERRUPTS >> 1); in rmw_vsie64()
3026 new_val |= vsbits << 1; in rmw_vsie64()
3278 new_val &= ~(VS_MODE_INTERRUPTS >> 1); in rmw_vsip64()
3279 new_val |= vsbits << 1; in rmw_vsip64()
[all …]
A Ddebug.c528 target_ulong new_val; in type2_reg_write() local
532 new_val = type2_mcontrol_validate(env, val); in type2_reg_write()
533 if (new_val != env->tdata1[index]) { in type2_reg_write()
534 env->tdata1[index] = new_val; in type2_reg_write()
644 target_ulong new_val; in type6_reg_write() local
649 if (new_val != env->tdata1[index]) { in type6_reg_write()
650 env->tdata1[index] = new_val; in type6_reg_write()
822 target_ulong new_val; in itrigger_reg_write() local
827 new_val = itrigger_validate(env, val); in itrigger_reg_write()
828 if (new_val != env->tdata1[index]) { in itrigger_reg_write()
[all …]
A Dcpu.h448 target_ulong *val, target_ulong new_val, target_ulong write_mask);
595 target_ulong new_val,
A Dcpu_helper.c764 target_ulong new_val, in riscv_cpu_set_aia_ireg_rmw_fn() argument
/qemu/hw/intc/
A Driscv_imsic.c92 target_ulong new_val, in riscv_imsic_eidelivery_rmw() argument
102 imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eidelivery_rmw()
110 target_ulong new_val, in riscv_imsic_eithreshold_rmw() argument
120 imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eithreshold_rmw()
127 target_ulong *val, target_ulong new_val, in riscv_imsic_topei_rmw() argument
183 if (new_val & mask) { in riscv_imsic_eix_rmw()
201 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_rmw() argument
237 new_val, wr_mask); in riscv_imsic_rmw()
240 new_val, wr_mask); in riscv_imsic_rmw()
246 true, val, new_val, wr_mask); in riscv_imsic_rmw()
[all …]
/qemu/hw/timer/
A Dhpet.c498 uint64_t old_val, new_val, cleared; in hpet_ram_write() local
516 new_val = deposit64(old_val, shift, len, value); in hpet_ram_write()
517 new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); in hpet_ram_write()
525 timer->config = new_val; in hpet_ram_write()
526 if (activating_bit(old_val, new_val, HPET_TN_ENABLE) in hpet_ram_write()
530 if (new_val & HPET_TN_32BIT) { in hpet_ram_write()
575 new_val = deposit64(old_val, shift, len, value); in hpet_ram_write()
576 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); in hpet_ram_write()
577 s->config = new_val; in hpet_ram_write()
608 new_val = value << shift; in hpet_ram_write()
[all …]
A Dexynos4210_pwm.c275 uint32_t new_val; in exynos4210_pwm_write() local
340 new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value); in exynos4210_pwm_write()
341 new_val &= ~(0x3E0 & value); in exynos4210_pwm_write()
344 if ((new_val & TINT_CSTAT_STATUS(i)) < in exynos4210_pwm_write()
350 s->reg_tint_cstat = new_val; in exynos4210_pwm_write()
/qemu/hw/core/
A Dregister.c74 uint64_t old_val, new_val, test, no_w_mask; in register_write() local
107 new_val = (val & ~no_w_mask) | (old_val & no_w_mask); in register_write()
108 new_val &= ~(val & ac->w1c); in register_write()
111 new_val = ac->pre_write(reg, new_val); in register_write()
116 new_val); in register_write()
119 register_write_val(reg, new_val); in register_write()
122 ac->post_write(reg, new_val); in register_write()
A Dqdev-properties-system.c41 const void *old_val, const char *new_val, in check_prop_still_unset() argument
52 prop->driver, prop->property, name, new_val); in check_prop_still_unset()
56 name, new_val); in check_prop_still_unset()
/qemu/hw/remote/
A Dproxy.c295 uint32_t orig_val, new_val, base_class, val; in probe_pci_info() local
342 new_val = 0xffffffff; in probe_pci_info()
343 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, in probe_pci_info()
345 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, in probe_pci_info()
347 size = (~(new_val & 0xFFFFFFF0)) + 1; in probe_pci_info()
350 type = (new_val & 0x1) ? in probe_pci_info()
/qemu/hw/display/
A Djazz_led.c66 uint8_t new_val = val & 0xff; in jazz_led_write() local
68 trace_jazz_led_write(addr, new_val); in jazz_led_write()
70 s->segments = new_val; in jazz_led_write()
/qemu/rust/hw/char/pl011/src/
A Ddevice.rs274 let new_val: registers::LineControl = value.into(); in write()
277 ^ bool::from(new_val.fifos_enabled()) in write()
281 if self.line_control.send_break() ^ new_val.send_break() { in write()
282 let mut break_enable: c_int = new_val.send_break().into(); in write()
294 self.line_control = new_val; in write()
/qemu/tests/tcg/multiarch/gdbstub/
A Dregisters.py187 new_val = frame.read_register(name)
192 if new_val != old_val:
/qemu/target/arm/
A Dptw.c738 uint64_t new_val, S1Translate *ptw, in arm_casq_ptw() argument
770 address_space_stq_be(as, ptw->out_phys, new_val, attrs, &result); in arm_casq_ptw()
779 cur_val = new_val; in arm_casq_ptw()
792 address_space_stq_le(as, ptw->out_phys, new_val, attrs, &result); in arm_casq_ptw()
801 cur_val = new_val; in arm_casq_ptw()
846 new_val = cpu_to_be64(new_val); in arm_casq_ptw()
847 cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); in arm_casq_ptw()
851 new_val = cpu_to_le64(new_val); in arm_casq_ptw()
852 cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); in arm_casq_ptw()
872 stq_be_p(host, new_val); in arm_casq_ptw()
[all …]
/qemu/hw/net/
A Dtulip.c712 uint32_t new_val) in tulip_csr9_write() argument
714 if (new_val & CSR9_SR) { in tulip_csr9_write()
716 !!(new_val & CSR9_SR_CS), in tulip_csr9_write()
717 !!(new_val & CSR9_SR_SK), in tulip_csr9_write()
718 !!(new_val & CSR9_SR_DI)); in tulip_csr9_write()
A Dtrace-events205 e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x"
206 e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x"
/qemu/hw/misc/
A Dxlnx-versal-crl.c77 #define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ argument
79 bool new_f = FIELD_EX32(new_val, reg, f); \
/qemu/target/hexagon/
A Dgenptr.c59 static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, in gen_masked_reg_write() argument
66 tcg_gen_andi_tl(new_val, new_val, ~reg_mask); in gen_masked_reg_write()
68 tcg_gen_or_tl(new_val, new_val, tmp); in gen_masked_reg_write()
/qemu/hw/xen/
A Dxen_pt_config_init.c1971 uint32_t new_val; in xen_pt_config_reg_init() local
1977 new_val = XEN_PT_MERGE_VALUE(val, data, host_mask) & size_mask; in xen_pt_config_reg_init()
1981 new_val |= ((val | data)) & ~size_mask; in xen_pt_config_reg_init()
1983 offset, data, val, new_val); in xen_pt_config_reg_init()
1984 val = new_val; in xen_pt_config_reg_init()
/qemu/tcg/
A Dtcg-op-ldst.c1157 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i32() argument
1170 tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); in do_nonatomic_op_i32()
1198 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i64() argument
1211 tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); in do_nonatomic_op_i64()
/qemu/include/exec/
A Dmemory.h902 int old_val, int new_val);
921 int old_val, int new_val);
/qemu/hw/i386/
A Dintel_iommu.c165 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_long() local
166 stl_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_long()
167 return new_val; in vtd_set_clear_mask_long()
173 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_quad() local
174 stq_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_quad()
175 return new_val; in vtd_set_clear_mask_quad()
/qemu/hw/ssi/
A Dxlnx-versal-ospi.c1248 static bool ind_wr_clearing_op_done(XlnxVersalOspi *s, uint64_t new_val) in ind_wr_clearing_op_done() argument
1252 bool set_in_new_val = FIELD_EX32(new_val, INDIRECT_WRITE_XFER_CTRL_REG, in ind_wr_clearing_op_done()

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