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Searched refs:page_bits (Results 1 – 16 of 16) sorted by relevance

/qemu/
A Dpage-target.c38 int page_bits = TARGET_PAGE_BITS; in qemu_target_pages_to_MiB() local
41 g_assert(page_bits < 20); in qemu_target_pages_to_MiB()
43 return pages >> (20 - page_bits); in qemu_target_pages_to_MiB()
/qemu/target/m68k/
A Dhelper.c736 int page_bits; in get_physical_address() local
870 page_bits = 13; in get_physical_address()
872 page_bits = 12; in get_physical_address()
874 *page_size = 1 << page_bits; in get_physical_address()
/qemu/accel/tcg/
A Dtranslate-all.c344 tcg_ctx->page_bits = TARGET_PAGE_BITS; in tb_gen_code()
/qemu/hw/nvme/
A Dnvme.h569 uint16_t page_bits; member
A Dctrl.c891 int num_prps = (len >> n->page_bits) + 1; in nvme_map_prp()
935 nents = (len + n->page_size - 1) >> n->page_bits; in nvme_map_prp()
7614 uint32_t page_bits = NVME_CC_MPS(cc) + 12; in nvme_start_ctrl() local
7615 uint32_t page_size = 1 << page_bits; in nvme_start_ctrl()
7665 n->page_bits = page_bits; in nvme_start_ctrl()
/qemu/include/tcg/
A Dtcg.h464 uint8_t page_bits; member
/qemu/tcg/ppc/
A Dtcg-target.c.inc2489 s->page_bits - CPU_TLB_ENTRY_BITS);
2492 s->page_bits - CPU_TLB_ENTRY_BITS);
2540 (32 - a_bits) & 31, 31 - s->page_bits);
2561 (32 - a_bits) & 31, 31 - s->page_bits);
2563 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits);
2566 64 - s->page_bits, s->page_bits - a_bits);
2567 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0);
/qemu/tcg/arm/
A Dtcg-target.c.inc1457 SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
1504 if (use_armv7_instructions && s->page_bits <= 16) {
1516 SHIFT_IMM_LSR(s->page_bits));
1519 SHIFT_IMM_LSL(s->page_bits));
/qemu/tcg/
A Dtcg-op-ldst.c42 tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits); in check_max_alignment()
/qemu/tcg/loongarch64/
A Dtcg-target.c.inc1011 s->page_bits - CPU_TLB_ENTRY_BITS);
1037 a_bits, s->page_bits - 1);
/qemu/tcg/mips/
A Dtcg-target.c.inc1247 s->page_bits - CPU_TLB_ENTRY_BITS);
1250 s->page_bits - CPU_TLB_ENTRY_BITS);
/qemu/tcg/aarch64/
A Dtcg-target.c.inc1769 mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32
1781 s->page_bits - CPU_TLB_ENTRY_BITS);
/qemu/tcg/sparc64/
A Dtcg-target.c.inc1095 s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL);
/qemu/tcg/i386/
A Dtcg-target.c.inc2181 if (s->page_bits + s->tlb_dyn_max_bits > 32) {
2190 s->page_bits - CPU_TLB_ENTRY_BITS);
/qemu/tcg/riscv/
A Dtcg-target.c.inc1731 s->page_bits - CPU_TLB_ENTRY_BITS);
/qemu/tcg/s390x/
A Dtcg-target.c.inc1888 s->page_bits - CPU_TLB_ENTRY_BITS);

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