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Searched refs:pstate (Results 1 – 25 of 32) sorted by relevance

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/qemu/qga/
A Dmain.c122 GAPersistentState pstate; member
854 g_assert(pstate); in set_persistent_state_defaults()
861 g_assert(pstate); in persistent_state_from_keyfile()
869 set_persistent_state_defaults(pstate); in persistent_state_from_keyfile()
872 pstate->fd_counter = in persistent_state_from_keyfile()
880 g_assert(pstate); in persistent_state_to_keyfile()
895 g_assert(pstate); in write_persistent_state()
933 g_assert(pstate); in read_persistent_state()
1007 handle = s->pstate.fd_counter++; in ga_get_fd_handle()
1011 if (s->pstate.fd_counter == INT64_MAX) { in ga_get_fd_handle()
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/qemu/bsd-user/aarch64/
A Dsignal.c125 uint32_t pstate = pstate_read(regs); in get_ucontext_sigreturn() local
129 if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t || in get_ucontext_sigreturn()
130 (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) { in get_ucontext_sigreturn()
A Dtarget_syscall.h45 uint64_t pstate; member
/qemu/tests/functional/acpi-bits/bits-tests/
A Dtestacpi.py2107 for index, pstate in enumerate(pss.pstates):
108 testsuite.print_detail("P[{}]: {}".format(index, pstate))
154 for n, pstate in enumerate(pss.pstates):
160 bits.wrmsr(apicid, IA32_PERF_CTL, pstate.control)
166 … turbo = (n == 0 and pstate.core_frequency == (pss.pstates[1].core_frequency + 1))
182 if aperf >= pstate.core_frequency:
185 if aperf == pstate.core_frequency:
189 …asured frequency {} >= expected {} MHz".format(n, aperf, pstate.core_frequency), aperf >= pstate.c…
191 …ed frequency {} MHz == expected {} MHz".format(n, aperf, pstate.core_frequency), aperf == pstate.c…
/qemu/target/sparc/
A Dwin_helper.c330 static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate) in get_gregset() argument
336 switch (pstate) { in get_gregset()
338 trace_win_helper_gregset_error(pstate); in get_gregset()
383 env->pstate = new_pstate; in cpu_change_pstate()
387 pstate_regs = env->pstate & 0xc01; in cpu_change_pstate()
401 env->pstate = new_pstate; in cpu_change_pstate()
A Dcpu.h516 uint32_t pstate; member
699 return env1->pstate & PS_PRIV; in cpu_supervisor_mode()
714 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { in cpu_interrupts_enabled()
768 if (env->pstate & PS_AM) { in cpu_get_tb_cpu_state()
771 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { in cpu_get_tb_cpu_state()
816 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | in sparc64_tstate()
A Dgdbstub.c93 ((env->pstate & 0xfff) << 8) | in sparc_cpu_gdb_read_register()
189 env->pstate = (tmp >> 8) & 0xfff; in sparc_cpu_gdb_write_register()
A Dtrace-events27 win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
A Dint64_helper.c187 env->pstate |= PS_RED; in sparc_cpu_do_interrupt()
226 env->pstate = PS_PEF | PS_PRIV; in sparc_cpu_do_interrupt()
A Dcpu.c53 env->pstate = PS_RMO | PS_PEF | PS_IE; in sparc_cpu_reset_hold()
63 env->pstate = PS_PRIV | PS_RED | PS_PEF; in sparc_cpu_reset_hold()
65 env->pstate |= PS_AG; in sparc_cpu_reset_hold()
663 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, in sparc_cpu_dump_state()
735 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 in sparc_cpu_mmu_index()
A Dmonitor.c151 { "pstate", offsetof(CPUSPARCState, pstate) },
A Dmmu_helper.c531 if (env->pstate & PS_PRIV) { in build_sfsr()
689 if (env->pstate & PS_PRIV) { in get_physical_address_code()
/qemu/target/arm/
A Darch_dump.c32 uint64_t pstate; member
241 uint64_t pstate, sp; in arm_cpu_write_elf64_note() local
251 pstate = cpsr_read(env); in arm_cpu_write_elf64_note()
254 pstate = pstate_read(env); in arm_cpu_write_elf64_note()
263 note.prstatus.pr_reg.pstate = cpu_to_dump64(s, pstate); in arm_cpu_write_elf64_note()
A Dinternals.h395 if (env->pstate & PSTATE_SP) { in aarch64_save_sp()
404 if (env->pstate & PSTATE_SP) { in aarch64_restore_sp()
417 if (!((imm ^ env->pstate) & PSTATE_SP)) { in update_spsel()
421 env->pstate = deposit32(env->pstate, 0, 1, imm); in update_spsel()
A Dcpu.c266 env->pstate = PSTATE_MODE_EL0t; in arm_cpu_reset_hold()
331 env->pstate = PSTATE_MODE_EL3h; in arm_cpu_reset_hold()
333 env->pstate = PSTATE_MODE_EL2h; in arm_cpu_reset_hold()
335 env->pstate = PSTATE_MODE_EL1h; in arm_cpu_reset_hold()
664 env->pstate = aarch64_pstate_mode(target_el, true); in arm_emulate_firmware_reset()
701 allIntMask = env->pstate & PSTATE_ALLINT || in arm_excp_unmasked()
703 (env->pstate & PSTATE_SP)); in arm_excp_unmasked()
/qemu/linux-user/aarch64/
A Dsignal.c32 uint64_t pstate; member
149 __put_user(pstate_read(env), &sf->uc.tuc_mcontext.pstate); in target_setup_general_frame()
260 uint64_t pstate; in target_restore_general_frame() local
272 __get_user(pstate, &sf->uc.tuc_mcontext.pstate); in target_restore_general_frame()
273 pstate_write(env, pstate); in target_restore_general_frame()
A Dtarget_syscall.h8 uint64_t pstate; member
/qemu/target/arm/tcg/
A Dhflags.c298 if (!(env->pstate & PSTATE_UAO)) { in rebuild_hflags_a64()
322 if (env->pstate & PSTATE_IL) { in rebuild_hflags_a64()
369 && !(env->pstate & PSTATE_TCO) in rebuild_hflags_a64()
386 && !(env->pstate & PSTATE_TCO) in rebuild_hflags_a64()
A Dtranslate.h365 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); in set_pstate_bits()
367 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); in set_pstate_bits()
377 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); in clear_pstate_bits()
379 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); in clear_pstate_bits()
A Dhelper-a64.c78 env->pstate |= PSTATE_ALLINT; in HELPER()
758 env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS); in cpsr_write_from_spsr_elx()
836 env->pstate &= ~PSTATE_SS; in HELPER()
856 env->pstate &= ~PSTATE_SS; in HELPER()
905 env->pstate |= PSTATE_IL; in HELPER()
911 env->pstate &= ~PSTATE_SS; in HELPER()
/qemu/tests/tcg/aarch64/
A Dbti-3.c10 uc->uc_mcontext.pstate = 1; in skip2_sigill()
A Dbti-1.c10 uc->uc_mcontext.pstate = 1; in skip2_sigill()
A Dbti-2.c19 uc->uc_mcontext.pstate = 1; in skip2_sigill()
/qemu/hw/usb/
A Dhcd-ehci.c253 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { in ehci_update_halt()
272 s->pstate = state; in ehci_set_state()
273 if (s->pstate == EST_INACTIVE) { in ehci_set_state()
284 return async ? s->astate : s->pstate; in ehci_get_state()
878 s->pstate = EST_INACTIVE; in ehci_reset()
1057 if (s->pstate == EST_INACTIVE) { in ehci_opreg_write()
2233 "Resetting to active\n", ehci->pstate); in ehci_advance_periodic_state()
2240 if (!ehci_enabled(ehci) && ehci->pstate == EST_INACTIVE) { in ehci_update_frindex()
2282 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { in ehci_work_bh()
2501 VMSTATE_UINT32(pstate, EHCIState),
A Dhcd-ehci.h300 uint32_t pstate; /* Current state in periodic schedule */ member

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