Home
last modified time | relevance | path

Searched refs:psw (Results 1 – 25 of 61) sorted by relevance

123

/qemu/target/hppa/
A Dhelper.c30 target_ulong psw; in cpu_hppa_get_psw() local
38 psw |= psw >> 3; in cpu_hppa_get_psw()
40 psw |= psw >> 6; in cpu_hppa_get_psw()
41 psw &= maskf; in cpu_hppa_get_psw()
43 psw |= psw >> 12; in cpu_hppa_get_psw()
50 psw = (psw & 0xff00000000ull) | ((psw & 0xff) << 8); in cpu_hppa_get_psw()
52 psw = (psw & 0xff) << 8; in cpu_hppa_get_psw()
57 psw |= env->psw | env->psw_xb; in cpu_hppa_get_psw()
59 return psw; in cpu_hppa_get_psw()
77 psw &= ~reserved; in cpu_hppa_put_psw()
[all …]
A Dsys_helper.c66 target_ulong psw = env->psw; in HELPER() local
76 env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); in HELPER()
77 return psw & PSW_SM; in HELPER()
91 mask = gva_offset_mask(env->psw); in HELPER()
A Dcpu.h211 uint32_t psw; /* All psw bits except the following: */ member
309 static inline uint64_t gva_offset_mask(target_ulong psw) in gva_offset_mask() argument
311 return (psw & PSW_W in gva_offset_mask()
316 static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, in hppa_form_gva_psw() argument
320 return off & gva_offset_mask(psw); in hppa_form_gva_psw()
322 return spc | (off & gva_offset_mask(psw)); in hppa_form_gva_psw()
329 return hppa_form_gva_psw(env->psw, spc, off); in hppa_form_gva()
A Dcpu.c46 return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), in hppa_cpu_get_pc()
82 flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); in cpu_get_tb_cpu_state()
136 if (env->psw & (ifetch ? PSW_C : PSW_D)) { in hppa_cpu_mmu_index()
137 return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); in hppa_cpu_mmu_index()
140 return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; in hppa_cpu_mmu_index()
/qemu/target/rx/
A Dcpu.h142 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
163 uint32_t psw = 0; in rx_cpu_pack_psw() local
164 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); in rx_cpu_pack_psw()
165 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); in rx_cpu_pack_psw()
166 psw = FIELD_DP32(psw, PSW, U, env->psw_u); in rx_cpu_pack_psw()
167 psw = FIELD_DP32(psw, PSW, I, env->psw_i); in rx_cpu_pack_psw()
168 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); in rx_cpu_pack_psw()
169 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); in rx_cpu_pack_psw()
170 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); in rx_cpu_pack_psw()
171 psw = FIELD_DP32(psw, PSW, C, env->psw_c); in rx_cpu_pack_psw()
[all …]
A Dhelper.c26 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) in rx_cpu_unpack_psw() argument
29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); in rx_cpu_unpack_psw()
32 env->psw_pm = FIELD_EX32(psw, PSW, PM); in rx_cpu_unpack_psw()
34 env->psw_u = FIELD_EX32(psw, PSW, U); in rx_cpu_unpack_psw()
35 env->psw_i = FIELD_EX32(psw, PSW, I); in rx_cpu_unpack_psw()
37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; in rx_cpu_unpack_psw()
38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; in rx_cpu_unpack_psw()
39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); in rx_cpu_unpack_psw()
40 env->psw_c = FIELD_EX32(psw, PSW, C); in rx_cpu_unpack_psw()
A Dgdbstub.c56 uint32_t psw; in rx_cpu_gdb_write_register() local
81 psw = ldl_p(mem_buf); in rx_cpu_gdb_write_register()
82 rx_cpu_unpack_psw(env, psw, 1); in rx_cpu_gdb_write_register()
A Dop_helper.c32 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) in _set_psw() argument
36 rx_cpu_unpack_psw(env, psw, rte); in _set_psw()
49 void helper_set_psw(CPURXState *env, uint32_t psw) in helper_set_psw() argument
51 _set_psw(env, psw, 0); in helper_set_psw()
54 void helper_set_psw_rte(CPURXState *env, uint32_t psw) in helper_set_psw_rte() argument
56 _set_psw(env, psw, 1); in helper_set_psw_rte()
/qemu/linux-user/s390x/
A Dcpu_loop.c80 env->psw.addr += env->int_svc_ilen; in cpu_loop()
85 env->psw.addr -= env->int_svc_ilen; in cpu_loop()
162 addr = env->psw.addr; in cpu_loop()
166 env->psw.addr += env->int_pgm_ilen; in cpu_loop()
189 env->psw.mask = regs->psw.mask; in target_cpu_copy_regs()
190 env->psw.addr = regs->psw.addr; in target_cpu_copy_regs()
A Dsignal.c37 target_psw_t psw; member
134 __put_user(psw_mask, &sregs->regs.psw.mask); in save_sigregs()
135 __put_user(env->psw.addr, &sregs->regs.psw.addr); in save_sigregs()
222 env->psw.mask = PSW_MASK_64 | PSW_MASK_32 | PSW_ASC_PRIMARY in setup_frame()
223 | (env->psw.mask & ~PSW_MASK_ASC); in setup_frame()
224 env->psw.addr = ka->_sa_handler; in setup_frame()
289 | (env->psw.mask & ~PSW_MASK_ASC); in setup_rt_frame()
290 env->psw.addr = ka->_sa_handler; in setup_rt_frame()
307 prev_addr = env->psw.addr; in restore_sigregs()
308 __get_user(mask, &sc->regs.psw.mask); in restore_sigregs()
[all …]
/qemu/target/s390x/tcg/
A Dexcp_helper.c43 env->psw.addr); in tcg_s390_program_interrupt()
159 if (!(env->psw.mask & PSW_MASK_64)) { in s390_cpu_tlb_fill()
165 if (!(env->psw.mask & PSW_MASK_64)) { in s390_cpu_tlb_fill()
255 env->psw.addr += ilen; in do_program_interrupt()
261 env->psw.addr); in do_program_interrupt()
327 if (!(env->psw.mask & PSW_MASK_EXT)) { in do_ext_interrupt()
390 g_assert(env->psw.mask & PSW_MASK_IO); in do_io_interrupt()
450 g_assert(env->psw.mask & PSW_MASK_MCHECK); in do_mchk_interrupt()
502 __func__, cs->exception_index, env->psw.mask, env->psw.addr); in s390_cpu_do_interrupt()
588 if (env->psw.mask & PSW_MASK_WAIT) { in s390_cpu_exec_interrupt()
[all …]
A Dcc_helper.c490 if (!(env->psw.mask & PSW_MASK_DAT)) { in HELPER()
496 env->psw.mask &= ~PSW_MASK_ASC; in HELPER()
497 env->psw.mask |= PSW_ASC_PRIMARY; in HELPER()
500 env->psw.mask &= ~PSW_MASK_ASC; in HELPER()
501 env->psw.mask |= PSW_ASC_SECONDARY; in HELPER()
504 if ((env->psw.mask & PSW_MASK_PSTATE) != 0) { in HELPER()
507 env->psw.mask &= ~PSW_MASK_ASC; in HELPER()
508 env->psw.mask |= PSW_ASC_HOME; in HELPER()
A Dcrypto_helper.c176 if (!(env->psw.mask & PSW_MASK_64)) { in cpacf_sha512()
178 message_reg_len = (env->psw.mask & PSW_MASK_32) ? 32 : 24; in cpacf_sha512()
254 if (!(env->psw.mask & PSW_MASK_64)) { in fill_buf_random()
256 buf_reg_len = (env->psw.mask & PSW_MASK_32) ? 32 : 24; in fill_buf_random()
/qemu/target/s390x/
A Dcpu.c70 uint64_t old_mask = env->psw.mask; in s390_cpu_set_psw()
73 env->psw.addr = addr; in s390_cpu_set_psw()
74 env->psw.mask = mask; in s390_cpu_set_psw()
101 uint64_t r = env->psw.mask; in s390_cpu_get_psw_mask()
119 cpu->env.psw.addr = value; in s390_cpu_set_pc()
126 return cpu->env.psw.addr; in s390_cpu_get_pc()
211 env->psw.mask &= ~PSW_MASK_RI; in s390_cpu_reset_hold()
328 if (env->psw.addr & 1) { in cpu_get_tb_cpu_state()
337 *pc = env->psw.addr; in cpu_get_tb_cpu_state()
340 flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; in cpu_get_tb_cpu_state()
[all …]
A Dhelper.c47 uint64_t asc = env->psw.mask & PSW_MASK_ASC; in s390_cpu_get_phys_page_debug()
51 if (!(env->psw.mask & PSW_MASK_64)) { in s390_cpu_get_phys_page_debug()
93 if (is_special_wait_psw(cpu->env.psw.addr)) { in s390_handle_wait()
129 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); in do_restart_interrupt()
149 if (!(env->psw.mask & PSW_MASK_PER)) { in s390_cpu_recompute_watchpoints()
180 PSW psw; /* 0x0100 */ member
224 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr); in s390_store_status()
225 sa->psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(&cpu->env)); in s390_store_status()
A Dcpu-sysemu.c50 cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; in s390_cpu_load_normal()
55 cpu->env.psw.mask ^= PSW_MASK_SHORTPSW; in s390_cpu_load_normal()
56 cpu->env.psw.addr = spsw & PSW_MASK_SHORT_ADDR; in s390_cpu_load_normal()
84 panic_info->u.s390.psw_mask = cpu->env.psw.mask; in s390_cpu_get_crash_info()
85 panic_info->u.s390.psw_addr = cpu->env.psw.addr; in s390_cpu_get_crash_info()
177 return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & in disabled_wait()
241 if (!tcg_enabled() || !(cpu->env.psw.mask & PSW_MASK_WAIT)) { in s390_cpu_set_state()
A Ds390x-internal.h123 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) | in get_per_atmid()
125 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) | in get_per_atmid()
126 ((env->psw.mask & PSW_MASK_DAT) ? (1 << 4) : 0) | in get_per_atmid()
127 ((env->psw.mask & PSW_ASC_SECONDARY) ? (1 << 3) : 0) | in get_per_atmid()
128 ((env->psw.mask & PSW_ASC_ACCREG) ? (1 << 2) : 0); in get_per_atmid()
133 if (!(env->psw.mask & PSW_MASK_64)) { in wrap_address()
134 if (!(env->psw.mask & PSW_MASK_32)) { in wrap_address()
A Dinterrupt.c148 if (!(env->psw.mask & PSW_MASK_MCHECK)) { in s390_cpu_has_mcck_int()
166 if (!(env->psw.mask & PSW_MASK_EXT)) { in s390_cpu_has_ext_int()
208 if (!(env->psw.mask & PSW_MASK_IO)) { in s390_cpu_has_io_int()
/qemu/tests/tcg/tricore/asm/
A Dmacros.h67 mfcr DREG_CALC_PSW, $psw; \
108 #define TEST_D_D_PSW(insn, num, result, psw, rs1) \ argument
109 TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument
125 TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument
133 TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
149 #define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \ argument
150 TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
/qemu/linux-user/include/host/s390x/
A Dhost-signal.h19 return uc->uc_mcontext.psw.addr; in host_signal_pc()
24 uc->uc_mcontext.psw.addr = pc; in host_signal_set_pc()
/qemu/pc-bios/s390-ccw/
A Djump2ipl.c20 void write_reset_psw(uint64_t psw) in write_reset_psw() argument
22 *reset_psw = psw; in write_reset_psw()
/qemu/docs/devel/
A Ds390-dasd-ipl.rst17 information: ``[psw][read ccw][tic ccw]``. When the machine executes the Read
40 location ``0x0`` thereby overwriting the IPL1 psw and channel program. This is ok
41 as long as the data placed in location ``0x0`` contains a psw whose instruction
48 The psw that was loaded into memory location ``0x0`` as part of the ipl process
50 psw's instruction address will point to the location in memory where we want
51 to start executing the operating system. This psw is loaded (via LPSW
63 procedure then loads the psw from ``0x0``.
107 So now IPL1's psw is at ``0x0`` and IPL1's channel program is at ``0x08``.
132 Now the operating system code is loaded somewhere in guest memory and the psw
/qemu/tests/tcg/i386/
A Dtest-i386-fprem.c150 static void psw(uint16_t sw) in psw() function
189 psw(sw); in do_fprem()
198 psw(sw); in do_fprem()
220 psw(sw); in do_fprem_stack_underflow()
/qemu/target/tricore/
A Dop_helper.c2418 (*psw)++; in cdc_increment()
2422 int count = *psw & mask; in cdc_increment()
2424 (*psw)--; in cdc_increment()
2438 int count = *psw & mask; in cdc_decrement()
2442 (*psw)--; in cdc_decrement()
2457 int count = *psw & mask; in cdc_zero()
2548 target_ulong psw; in helper_call() local
2550 psw = psw_read(env); in helper_call()
2564 psw |= MASK_PSW_CDE; in helper_call()
2603 psw_write(env, psw); in helper_call()
[all …]
/qemu/tests/tcg/tricore/c/
A Dcrt0-tc2x.S75 mfcr %d0,$psw
78 mtcr $psw,%d0
85 mfcr %d0,$psw
87 mtcr $psw,%d0
109 mfcr %d0,$psw
111 mtcr $psw,%d0

Completed in 68 milliseconds

123