Searched refs:rcc (Results 1 – 8 of 8) sorted by relevance
| /qemu/target/rx/ |
| A D | cpu.c | 76 RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); in rx_cpu_reset_hold() local
80 if (rcc->parent_phases.hold) { in rx_cpu_reset_hold()
81 rcc->parent_phases.hold(obj, type); in rx_cpu_reset_hold()
124 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); in rx_cpu_realize() local
136 rcc->parent_realize(dev, errp); in rx_cpu_realize()
211 RXCPUClass *rcc = RX_CPU_CLASS(klass); in rx_cpu_class_init() local
215 &rcc->parent_realize); in rx_cpu_class_init()
217 &rcc->parent_phases); in rx_cpu_class_init()
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| /qemu/hw/arm/ |
| A D | stm32l4x5_soc.c | 146 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC); in stm32l4x5_soc_initfn()
206 qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-fclk-out")); in stm32l4x5_soc_realize()
208 qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-refclk-out")); in stm32l4x5_soc_realize()
230 qdev_get_clock_out(DEVICE(&(s->rcc)), name)); in stm32l4x5_soc_realize()
240 qdev_get_clock_out(DEVICE(&(s->rcc)), "syscfg-out")); in stm32l4x5_soc_realize()
309 busdev = SYS_BUS_DEVICE(&s->rcc); in stm32l4x5_soc_realize()
322 qdev_get_clock_out(DEVICE(&(s->rcc)), name)); in stm32l4x5_soc_realize()
338 qdev_get_clock_out(DEVICE(&(s->rcc)), name)); in stm32l4x5_soc_realize()
352 qdev_get_clock_out(DEVICE(&(s->rcc)), "lpuart1-out")); in stm32l4x5_soc_realize()
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| A D | stm32f405_soc.c | 63 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC); in stm32f405_soc_initfn()
167 dev = DEVICE(&s->rcc); in stm32f405_soc_realize()
168 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rcc), errp)) { in stm32f405_soc_realize()
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| A D | stellaris.c | 78 uint32_t rcc; member
210 return s->rcc; in ssys_read()
214 xtal = (s->rcc >> 6) & 0xf; in ssys_read()
280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); in ssys_calculate_system_clock()
315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
319 s->rcc = value; in ssys_write()
385 s->rcc = 0x078e3ac0; in stellaris_sys_reset_enter()
429 VMSTATE_UINT32(rcc, ssys_state),
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| /qemu/tests/qtest/ |
| A D | cmsdk-apb-watchdog-test.c | 125 uint32_t rcc; in test_clock_change() local
146 rcc = readl(SSYS_BASE + RCC); in test_clock_change()
147 g_assert_cmphex(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); in test_clock_change()
148 rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); in test_clock_change()
149 writel(SSYS_BASE + RCC, rcc); in test_clock_change()
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| /qemu/include/hw/arm/ |
| A D | stm32l4x5_soc.h | 56 Stm32l4x5RccState rcc; member
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| A D | stm32f405_soc.h | 59 STM32RccState rcc; member
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| /qemu/target/riscv/ |
| A D | cpu.c | 741 RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu); in riscv_cpu_get_name() local
742 const char *typename = object_class_get_name(OBJECT_CLASS(rcc)); in riscv_cpu_get_name()
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