Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 461) sorted by relevance

12345678910>>...19

/qemu/include/hw/
A Dregisterfields.h23 enum { R_ ## reg = (addr) / 4 };
27 enum { R_ ## reg = (addr) };
31 enum { R_ ## reg = (addr) / 2 };
35 enum { R_ ## reg = (addr) / 8 };
51 R_ ## reg ## _ ## field ## _LENGTH)
54 R_ ## reg ## _ ## field ## _LENGTH)
57 R_ ## reg ## _ ## field ## _LENGTH)
77 FIELD_EX32((regs)[R_ ## reg], reg, field)
79 FIELD_EX64((regs)[R_ ## reg], reg, field)
153 (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
[all …]
/qemu/tests/qtest/
A Driscv-iommu-test.c59 uint32_t reg; in test_reg_reset() local
66 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0); in test_reg_reset()
72 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FIE, ==, 0); in test_reg_reset()
84 g_assert_cmpuint(reg & RISCV_IOMMU_DDTP_MODE, ==, in test_reg_reset()
88 g_assert_cmpuint(reg, ==, 0); in test_reg_reset()
101 uint32_t reg; in qtest_wait_for_queue_active() local
107 if (reg & RISCV_IOMMU_QUEUE_ACTIVE) { in qtest_wait_for_queue_active()
123 uint32_t reg; in test_iommu_init_queues() local
154 reg |= RISCV_IOMMU_CQCSR_CQEN; in test_iommu_init_queues()
175 reg |= RISCV_IOMMU_FQCSR_FQEN; in test_iommu_init_queues()
[all …]
A Dqtest_aspeed.c19 uint8_t slave_addr, uint8_t reg) in aspeed_i2c_startup() argument
38 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg); in aspeed_i2c_startup()
44 uint8_t reg, size_t nbytes) in aspeed_i2c_read_n() argument
50 aspeed_i2c_startup(s, baseaddr, slave_addr, reg); in aspeed_i2c_read_n()
87 aspeed_i2c_startup(s, baseaddr, slave_addr, reg); in aspeed_i2c_write_n()
100 uint8_t reg, uint32_t v) in aspeed_i2c_writel() argument
102 aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v)); in aspeed_i2c_writel()
107 uint8_t reg, uint16_t v) in aspeed_i2c_writew() argument
109 aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v)); in aspeed_i2c_writew()
114 uint8_t reg, uint8_t v) in aspeed_i2c_writeb() argument
[all …]
A Dahci-test.c479 uint32_t reg; in ahci_test_hba_spec() local
525 g_assert_cmphex(reg, ==, 0); in ahci_test_hba_spec()
545 switch (reg) { in ahci_test_hba_spec()
570 g_assert_cmphex(reg, ==, 0); in ahci_test_hba_spec()
595 g_assert_cmphex(reg, ==, 0); in ahci_test_hba_spec()
645 uint32_t reg; in ahci_test_port_spec() local
670 g_assert_cmphex(reg, ==, 0); in ahci_test_port_spec()
674 g_assert_cmphex(reg, ==, 0); in ahci_test_port_spec()
716 g_assert_cmphex(reg, ==, 0); in ahci_test_port_spec()
744 g_assert_cmphex(reg, ==, 0); in ahci_test_port_spec()
[all …]
A Dm48t59-test.c48 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_read_ioio()
54 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_write_ioio()
58 static uint8_t cmos_read(QTestState *s, uint8_t reg) in cmos_read() argument
61 return cmos_read_mmio(s, reg); in cmos_read()
63 return cmos_read_ioio(s, reg); in cmos_read()
70 cmos_write_mmio(s, reg, val); in cmos_write()
72 cmos_write_ioio(s, reg, val); in cmos_write()
223 uint8_t reg, val; in fuzz_registers() local
228 if (reg == 7) { in fuzz_registers()
233 cmos_write(s, reg, val); in fuzz_registers()
[all …]
/qemu/hw/char/
A Dexynos4210_uart.c67 #define I_(reg) (reg / sizeof(uint32_t)) argument
227 level = reg * 32; in exynos4210_uart_FIFO_trigger_level()
231 level = reg * 8; in exynos4210_uart_FIFO_trigger_level()
235 level = reg * 2; in exynos4210_uart_FIFO_trigger_level()
248 uint32_t reg; in exynos4210_uart_Tx_FIFO_trigger_level() local
250 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> in exynos4210_uart_Tx_FIFO_trigger_level()
259 uint32_t reg; in exynos4210_uart_Rx_FIFO_trigger_level() local
261 reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >> in exynos4210_uart_Rx_FIFO_trigger_level()
315 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; in exynos4210_uart_update_irq()
317 if (s->reg[I_(UINTP)]) { in exynos4210_uart_update_irq()
[all …]
A Dnrf51_uart.c29 irq |= (s->reg[R_UART_RXDRDY] && in nrf51_uart_update_irq()
31 irq |= (s->reg[R_UART_TXDRDY] && in nrf51_uart_update_irq()
33 irq |= (s->reg[R_UART_ERROR] && in nrf51_uart_update_irq()
35 irq |= (s->reg[R_UART_RXTO] && in nrf51_uart_update_irq()
66 r = s->reg[R_UART_INTEN]; in uart_read()
69 r = s->reg[addr / 4]; in uart_read()
100 s->reg[R_UART_TXDRDY] = 1; in uart_transmit()
142 s->reg[addr / 4] = value; in uart_write()
187 s->reg[addr / 4] = value; in uart_write()
207 memset(s->reg, 0, sizeof(s->reg)); in nrf51_uart_reset()
[all …]
/qemu/target/xtensa/
A Dgdbstub.c69 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; in xtensa_cpu_gdb_read_register() local
81 switch (reg->type) { in xtensa_cpu_gdb_read_register()
97 i = reg->targno & 0x0f; in xtensa_cpu_gdb_read_register()
98 switch (reg->size) { in xtensa_cpu_gdb_read_register()
124 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; in xtensa_cpu_gdb_write_register() local
137 switch (reg->type) { in xtensa_cpu_gdb_write_register()
148 env->sregs[reg->targno & 0xff] = tmp; in xtensa_cpu_gdb_write_register()
156 switch (reg->size) { in xtensa_cpu_gdb_write_register()
166 return reg->size; in xtensa_cpu_gdb_write_register()
170 env->regs[reg->targno & 0x0f] = tmp; in xtensa_cpu_gdb_write_register()
[all …]
/qemu/hw/core/
A Dregister.c77 assert(reg); in register_write()
79 ac = reg->access; in register_write()
87 old_val = reg->data ? register_read_val(reg) : ac->reset; in register_write()
132 assert(reg); in register_read()
141 ret = reg->data ? register_read_val(reg) : ac->reset; in register_read()
164 g_assert(reg); in register_reset()
166 if (!reg->data || !reg->access) { in register_reset()
172 register_write_val(reg, reg->access->reset); in register_reset()
175 ac->post_write(reg, reg->access->reset); in register_reset()
194 if (!reg) { in register_write_memory()
[all …]
/qemu/hw/intc/
A Darm_gicv3_kvm.c179 uint32_t reg; in kvm_dist_get_edge_trigger() local
192 reg = half_unshuffle32(reg >> 1); in kvm_dist_get_edge_trigger()
194 reg = (reg << 16); in kvm_dist_get_edge_trigger()
204 uint32_t reg; in kvm_dist_put_edge_trigger() local
218 reg = (reg & 0xffff0000) >> 16; in kvm_dist_put_edge_trigger()
220 reg = reg & 0xffff; in kvm_dist_put_edge_trigger()
222 reg = half_shuffle32(reg) << 1; in kvm_dist_put_edge_trigger()
230 uint32_t reg; in kvm_gic_get_line_level_bmp() local
241 uint32_t reg; in kvm_gic_put_line_level_bmp() local
253 uint32_t reg; in kvm_dist_getbmp() local
[all …]
A Darm_gic_kvm.c235 uint32_t reg; in kvm_dist_get() local
263 uint32_t reg; in kvm_dist_put() local
275 reg = 0; in kvm_dist_put()
278 reg = deposit32(reg, j * width, width, field); in kvm_dist_put()
290 uint32_t reg; in kvm_arm_gic_put() local
305 reg = s->ctlr; in kvm_arm_gic_put()
366 reg = s->cpu_ctlr[cpu]; in kvm_arm_gic_put()
383 reg = s->apr[i][cpu]; in kvm_arm_gic_put()
391 uint32_t reg; in kvm_arm_gic_get() local
401 s->ctlr = reg; in kvm_arm_gic_get()
[all …]
/qemu/hw/misc/
A Dimx31_ccm.c38 switch (reg) { in imx31_ccm_reg_name()
217 s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d; in imx31_ccm_reset()
218 s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48; in imx31_ccm_reset()
219 s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f; in imx31_ccm_reset()
220 s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000; in imx31_ccm_reset()
221 s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800; in imx31_ccm_reset()
241 value = s->reg[offset >> 2]; in imx31_ccm_read()
269 s->reg[IMX31_CCM_PDR1_REG] = value; in imx31_ccm_write()
278 s->reg[IMX31_CCM_CGR0_REG] = value; in imx31_ccm_write()
281 s->reg[IMX31_CCM_CGR1_REG] = value; in imx31_ccm_write()
[all …]
A Dimx25_ccm.c36 switch (reg) { in imx25_ccm_reg_name()
201 s->reg[IMX25_CCM_MPCTL_REG] = 0x800b2c01; in imx25_ccm_reset()
202 s->reg[IMX25_CCM_UPCTL_REG] = 0x84042800; in imx25_ccm_reset()
207 s->reg[IMX25_CCM_CCTL_REG] = 0xd0030000; in imx25_ccm_reset()
208 s->reg[IMX25_CCM_CGCR0_REG] = 0x028A0100; in imx25_ccm_reset()
209 s->reg[IMX25_CCM_CGCR1_REG] = 0x04008100; in imx25_ccm_reset()
210 s->reg[IMX25_CCM_CGCR2_REG] = 0x00000438; in imx25_ccm_reset()
211 s->reg[IMX25_CCM_PCDR0_REG] = 0x01010101; in imx25_ccm_reset()
212 s->reg[IMX25_CCM_PCDR1_REG] = 0x01010101; in imx25_ccm_reset()
235 value = s->reg[offset >> 2]; in imx25_ccm_read()
[all …]
/qemu/hw/xen/
A Dxen_pt_config_init.c89 reg = reg_entry->reg; in xen_pt_find_reg()
132 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_byte_reg_read() local
145 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_word_reg_read() local
158 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_long_reg_read() local
175 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_byte_reg_write() local
194 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_word_reg_write() local
213 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_long_reg_write() local
318 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_cmd_reg_write() local
436 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_bar_reg_read() local
476 XenPTRegInfo *reg = cfg_entry->reg; in xen_pt_bar_reg_write() local
[all …]
/qemu/hw/timer/
A Dexynos4210_mct.c199 } reg; member
241 } reg; member
381 return s->reg.cnt + count; in exynos4210_gfrc_get_count()
504 if (s->g_timer.reg.comp[id] - s->g_timer.reg.cnt < MCT_GT_COUNTER_STEP) { in exynos4210_gcomp_get_distance()
505 return s->g_timer.reg.comp[id] - s->g_timer.reg.cnt; in exynos4210_gcomp_get_distance()
575 if (s->g_timer.reg.cnt == s->g_timer.reg.comp[i]) { in exynos4210_gfrc_event()
582 s->g_timer.reg.comp[i] += s->g_timer.reg.comp_add_incr[i]; in exynos4210_gfrc_event()
1031 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg)); in exynos4210_mct_reset()
1037 memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt)); in exynos4210_mct_reset()
1038 memset(s->l_timer[1].reg.cnt, 0, sizeof(s->l_timer[1].reg.cnt)); in exynos4210_mct_reset()
[all …]
/qemu/target/ppc/
A Dmem_helper.c92 for (; reg < 32; reg++) { in helper_lmw()
98 for (; reg < 32; reg++) { in helper_lmw()
114 for (; reg < 32; reg++) { in helper_stmw()
120 for (; reg < 32; reg++) { in helper_stmw()
145 reg = (reg + 1) % 32; in do_lsw()
165 reg = (reg + 1) % 32; in do_lsw()
234 reg = (reg + 1) % 32; in helper_stsw()
253 reg = (reg + 1) % 32; in helper_stsw()
360 if (likely(reg != rb && (ra == 0 || reg != ra))) { in helper_lscbx()
370 reg++; in helper_lscbx()
[all …]
/qemu/hw/net/fsl_etsec/
A Detsec.c89 switch (reg->access) { in etsec_read()
98 ret = reg->value; in etsec_read()
104 ret, addr, reg->name, reg->desc); in etsec_read()
124 reg->value &= ~value; in write_tstat()
142 reg->value &= ~value; in write_rstat()
150 reg->value = value & ~0x7; in write_tbasex()
172 reg->value = value; in write_dmactrl()
219 before = reg->value; in etsec_write()
224 reg->value &= ~value; in etsec_write()
230 reg->value = value; in etsec_write()
[all …]
/qemu/target/i386/tcg/sysemu/
A Dbpt_helper.c170 int reg; in check_hw_breakpoints() local
174 for (reg = 0; reg < DR7_MAX_BP; reg++) { in check_hw_breakpoints()
195 dr6 |= 1 << reg; in check_hw_breakpoints()
239 if (reg >= 4 && reg < 6) { in helper_get_dr()
243 reg += 2; in helper_get_dr()
253 return env->dr[reg]; in helper_get_dr()
258 if (reg >= 4 && reg < 6) { in helper_set_dr()
262 reg += 2; in helper_set_dr()
272 if (reg < 4) { in helper_set_dr()
276 env->dr[reg] = t0; in helper_set_dr()
[all …]
/qemu/target/arm/
A Dgdbstub.c117 if (reg < nregs) { in vfp_gdb_get_reg()
123 if (reg < nregs) { in vfp_gdb_get_reg()
141 if (reg < nregs) { in vfp_gdb_set_reg()
167 switch (reg) { in vfp_gdb_get_sysreg()
181 switch (reg) { in vfp_gdb_set_sysreg()
197 switch (reg) { in mve_gdb_get_reg()
210 switch (reg) { in mve_gdb_set_reg()
344 switch (reg) { in m_sysreg_ptr()
412 int reg = 0; in arm_gen_dynamic_m_systemreg_feature() local
441 return m_sysreg_get(env, buf, reg >> 1, reg & 1); in arm_gdb_get_m_secextreg()
[all …]
A Dgdbstub64.c86 switch (reg) { in aarch64_gdb_get_fpu_reg()
109 switch (reg) { in aarch64_gdb_set_fpu_reg()
136 switch (reg) { in aarch64_gdb_get_sve_reg()
155 int preg = reg - 34; in aarch64_gdb_get_sve_reg()
186 switch (reg) { in aarch64_gdb_set_sve_reg()
207 int preg = reg - 34; in aarch64_gdb_set_sve_reg()
232 switch (reg) { in aarch64_gdb_get_pauth_reg()
249 bool is_high = reg & 2; in aarch64_gdb_get_pauth_reg()
346 int reg = 0; in arm_gen_dynamic_svereg_feature() local
398 assert(reg == 0); in aarch64_gdb_get_tag_ctl_reg()
[all …]
/qemu/target/riscv/kvm/
A Dkvm-cpu.c238 uint64_t id, reg; in kvm_riscv_update_cpu_misa_ext() local
250 reg = 0; in kvm_riscv_update_cpu_misa_ext()
430 uint64_t id, reg; in kvm_riscv_update_cpu_cfg_isa_ext() local
562 target_ulong reg; in kvm_riscv_get_regs_core() local
569 env->pc = reg; in kvm_riscv_get_regs_core()
590 reg = env->pc; in kvm_riscv_put_regs_core()
726 uint64_t reg; in kvm_riscv_put_regs_timer() local
763 uint64_t reg; in kvm_riscv_get_timebase_frequency() local
767 return reg; in kvm_riscv_get_timebase_frequency()
792 env->vl = reg; in kvm_riscv_get_regs_vector()
[all …]
/qemu/contrib/plugins/
A Dexeclog.c97 sz = qemu_plugin_read_register(reg->handle, reg->new); in insn_check_regs()
98 g_assert(sz == reg->last->len); in insn_check_regs()
100 if (memcmp(reg->last->data, reg->new->data, sz)) { in insn_check_regs()
101 GByteArray *temp = reg->last; in insn_check_regs()
108 reg->last = reg->new; in insn_check_regs()
109 reg->new = temp; in insn_check_regs()
304 reg->handle = desc->handle; in init_vcpu_register()
306 reg->last = g_byte_array_new(); in init_vcpu_register()
307 reg->new = g_byte_array_new(); in init_vcpu_register()
310 r = qemu_plugin_read_register(reg->handle, reg->last); in init_vcpu_register()
[all …]
/qemu/hw/ppc/
A Dspapr_vio.c75 if (dev->reg == reg) { in spapr_vio_find_by_reg()
162 target_ulong reg = args[0]; in h_reg_crq() local
218 target_ulong reg = args[0]; in h_free_crq() local
232 target_ulong reg = args[0]; in h_send_crq() local
255 target_ulong reg = args[0]; in h_enable_crq() local
397 if (other != dev && other->reg == dev->reg) { in reg_conflict()
448 irq = reg & 0xff; in spapr_vio_reg_to_irq()
477 if (dev->reg != -1) { in spapr_vio_busdev_realize()
549 target_ulong reg = args[0]; in h_vio_signal() local
667 if (dev1->reg < dev2->reg) { in type_init()
[all …]
A Dpnv_nest_pervasive.c50 uint32_t reg = addr >> 3; in pnv_chiplet_ctrl_read() local
55 if (reg == i) { in pnv_chiplet_ctrl_read()
57 } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) { in pnv_chiplet_ctrl_read()
65 switch (reg) { in pnv_chiplet_ctrl_read()
73 __func__, reg); in pnv_chiplet_ctrl_read()
108 uint32_t reg = addr >> 3; in pnv_chiplet_ctrl_write() local
112 if (reg == i) { in pnv_chiplet_ctrl_write()
115 } else if (reg == (i + 0x10)) { in pnv_chiplet_ctrl_write()
118 } else if (reg == (i + 0x20)) { in pnv_chiplet_ctrl_write()
124 switch (reg) { in pnv_chiplet_ctrl_write()
[all …]
/qemu/tests/qtest/libqos/
A Di2c.c23 void i2c_read_block(QI2CDevice *i2cdev, uint8_t reg, in i2c_read_block() argument
26 qi2c_send(i2cdev, &reg, 1); in i2c_read_block()
30 void i2c_write_block(QI2CDevice *i2cdev, uint8_t reg, in i2c_write_block() argument
34 cmd[0] = reg; in i2c_write_block()
40 uint8_t i2c_get8(QI2CDevice *i2cdev, uint8_t reg) in i2c_get8() argument
43 i2c_read_block(i2cdev, reg, resp, sizeof(resp)); in i2c_get8()
47 uint16_t i2c_get16(QI2CDevice *i2cdev, uint8_t reg) in i2c_get16() argument
50 i2c_read_block(i2cdev, reg, resp, sizeof(resp)); in i2c_get16()
54 void i2c_set8(QI2CDevice *i2cdev, uint8_t reg, uint8_t value) in i2c_set8() argument
56 i2c_write_block(i2cdev, reg, &value, 1); in i2c_set8()
[all …]

Completed in 87 milliseconds

12345678910>>...19