Searched refs:reg_index (Results 1 – 8 of 8) sorted by relevance
| /qemu/hw/net/fsl_etsec/ |
| A D | etsec.c | 80 uint32_t reg_index = addr / 4; in etsec_read() local
84 assert(reg_index < ETSEC_REG_NUMBER); in etsec_read()
86 reg = &etsec->regs[reg_index]; in etsec_read()
111 uint32_t reg_index, in write_tstat() argument
129 uint32_t reg_index, in write_rstat() argument
147 uint32_t reg_index, in write_tbasex() argument
212 uint32_t reg_index = addr / 4; in etsec_write() local
216 assert(reg_index < ETSEC_REG_NUMBER); in etsec_write()
218 reg = &etsec->regs[reg_index]; in etsec_write()
221 switch (reg_index) { in etsec_write()
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| A D | miim.c | 90 uint32_t reg_index, in etsec_write_miim() argument
94 switch (reg_index) { in etsec_write_miim()
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| A D | etsec.h | 149 uint32_t reg_index,
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| /qemu/target/riscv/ |
| A D | pmp.c | 466 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, in pmpcfg_csr_write() argument
474 trace_pmpcfg_csr_write(env->mhartid, reg_index, val); in pmpcfg_csr_write()
478 modified |= pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); in pmpcfg_csr_write()
492 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) in pmpcfg_csr_read() argument
500 val = pmp_read_cfg(env, (reg_index * 4) + i); in pmpcfg_csr_read()
503 trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); in pmpcfg_csr_read()
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| A D | trace-events | 5 pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" P…
6 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%"…
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| A D | pmp.h | 67 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
69 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
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| A D | csr.c | 566 uint32_t reg_index = csrno - CSR_PMPCFG0; in pmp() local
569 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { in pmp()
4251 uint32_t reg_index = csrno - CSR_PMPCFG0; in read_pmpcfg() local
4253 *val = pmpcfg_csr_read(env, reg_index); in read_pmpcfg()
4260 uint32_t reg_index = csrno - CSR_PMPCFG0; in write_pmpcfg() local
4262 pmpcfg_csr_write(env, reg_index, val); in write_pmpcfg()
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| /qemu/hw/display/ |
| A D | cirrus_vga.c | 1484 switch (reg_index) { in cirrus_vga_read_gr()
1501 if (reg_index < 0x3a) { in cirrus_vga_read_gr()
1502 return s->vga.gr[reg_index]; in cirrus_vga_read_gr()
1514 switch (reg_index) { in cirrus_vga_write_gr()
1516 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1520 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1529 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; in cirrus_vga_write_gr()
1537 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1543 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
1570 s->vga.gr[reg_index] = reg_value; in cirrus_vga_write_gr()
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