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Searched refs:registers (Results 1 – 25 of 97) sorted by relevance

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/qemu/hw/dma/
A Dxlnx_dpdma.c292 flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR])) in xlnx_dpdma_update_irq()
293 || (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR]))); in xlnx_dpdma_update_irq()
411 return s->registers[offset]; in xlnx_dpdma_read()
515 s->registers[offset] = value; in xlnx_dpdma_write()
520 s->registers[offset] = value; in xlnx_dpdma_write()
525 s->registers[offset] = value; in xlnx_dpdma_write()
530 s->registers[offset] = value; in xlnx_dpdma_write()
535 s->registers[offset] = value; in xlnx_dpdma_write()
540 s->registers[offset] = value; in xlnx_dpdma_write()
545 s->registers[offset] = value; in xlnx_dpdma_write()
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/qemu/contrib/plugins/
A Dexeclog.c29 GPtrArray *registers; member
92 for (int n = 0; n < cpu->registers->len; n++) { in insn_check_regs()
93 Register *reg = cpu->registers->pdata[n]; in insn_check_regs()
121 if (cpu->registers) { in vcpu_insn_exec_with_regs()
142 if (cpu->registers) { in vcpu_insn_exec_only_regs()
335 g_autoptr(GPtrArray) registers = g_ptr_array_new(); in registers_init()
352 g_ptr_array_add(registers, reg); in registers_init()
367 return registers->len ? g_steal_pointer(&registers) : NULL; in registers_init()
391 c->registers = registers_init(vcpu_index); in vcpu_init()
/qemu/tests/tcg/multiarch/system/
A DMakefile.softmmu-target52 run-gdbstub-registers: memory
56 --output $<.registers.gdb.out \
59 --bin $< --test $(MULTIARCH_SRC)/gdbstub/registers.py, \
67 run-gdbstub-untimely-packet run-gdbstub-registers
/qemu/docs/specs/
A Dstandard-vga.rst80 port first), so indexed registers can be updated with a single
83 bochs dispi interface registers, mapped flat without index/data ports.
86 QEMU extended registers. QEMU 2.2+ only.
87 The pci revision is 2 (or greater) when these registers are present.
88 The registers are 32bit.
A Dvmw_pvscsi-spec.rst17 The shared memory consists of a registers area and a rings area.
18 The registers area is used to raise hypervisor interrupts and issue device
26 The length of the registers area is 1 page
28 registers area is described by the ``PVSCSIRegOffset`` enum. There
29 are registers to issue device commands (with optional short data),
A Dacpi_cpu_hotplug.rst11 Legacy ACPI CPU hotplug interface registers
27 Modern ACPI CPU hotplug interface registers
39 All accesses to registers described below, imply little-endian byte order.
41 Reserved registers behavior:
114 registers will read/store data from/to selected CPU.
182 with current values of OST event and status registers.
224 a valid state and that access to other registers won't be ignored.
A Dppc-xive.rst69 tctx: Thread interrupt Context registers
133 Interrupt Management context. This context is a set of registers which
145 The Thread Interrupt Management registers are accessible through a
148 registers. First page (page address ending in ``0b00``) gives access
196 four sets of registers, one for each exception that can be delivered
199 Management Area (TIMA), which exposes the thread context registers to
A Dacpi_mem_hotplug.rst49 All following accesses to other registers in 0xa00-0xa17
83 - write accesses to memory hot-plug registers not documented above are ignored
84 - read accesses to memory hot-plug registers not documented above return
A Dacpi_hest_ghes.rst65 contains an address registers table and an Error Status Data Block table.
67 (3) The address registers table contains N Error Block Address entries
80 corresponding "address registers" in the "etc/hardware_errors" blob.
A Drocker.rst50 Each switch instance registers as a PCI device with PCI configuration space::
86 All registers are 4 or 8 bytes long. It is assumed host software will access 4
87 byte registers with one 4-byte access, and 8 byte registers with either two
95 0x0000-0x000f Bogus registers to catch misbehaving
98 0x0010-0x00ff Test registers
99 0x0300-0x03ff General purpose registers
102 Holes in register space are reserved. Writes to reserved registers do nothing.
103 Reads to reserved registers read back as 0.
105 No fancy stuff like write-combining is enabled on any of the registers.
172 byte boundary. Each descriptor ring will have these registers::
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A Divshmem-spec.rst31 - BAR0 holds device registers (256 Byte MMIO)
56 PCI device registers
59 BAR 0 contains the following registers:
78 Software should only access the registers as specified in column
/qemu/rust/hw/char/pl011/src/
A Ddevice.rs20 registers::{self, Interrupt},
65 pub flags: registers::Flags,
67 pub line_control: registers::LineControl,
69 pub receive_status_error_clear: registers::ReceiveStatusErrorClear,
71 pub control: registers::Control,
203 self.int_level &= !registers::INT_RX; in read()
254 self.int_level |= registers::INT_TX; in write()
274 let new_val: registers::LineControl = value.into(); in write()
464 matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) in fifo_enabled()
493 self.int_level |= registers::INT_RX; in put_fifo()
/qemu/docs/devel/
A Dsecure-coding-practices.rst73 The guest may access device registers in unusual orders or at unexpected
76 may make nonsense accesses to device registers such as starting operations
82 certain device registers. Device emulation code must handle the case where the
83 guest overwrites registers or submits further requests before an ongoing
A Dtcg-ops.rst126 of the integer registers for the host. This may be larger
893 registers using the following ops:
905 - 64-bit registers can hold 32-bit values
908 - all 32-bit TCG ops ignore the high part of 64-bit registers
931 used by each backend to indicate all registers.
935 The mov_i32 and mov_i64 operations must accept any registers of the
953 - The first N parameters are passed in registers.
955 - Some registers are clobbered during the call.
956 - The function can return 0 or 1 value in registers. On a 32 bit
965 often modified, e.g. the integer registers and the condition
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/qemu/target/arm/tcg/
A Dt16.decode42 # Data-processing (two low registers)
141 # Add/subtract (three low registers)
149 # Add/subtract (two low registers and immediate)
168 # Add, compare, move (two high registers)
/qemu/tests/tcg/multiarch/
A DMakefile.target98 run-gdbstub-registers: sha512
102 --bin $< --test $(MULTIARCH_SRC)/gdbstub/registers.py, \
139 run-gdbstub-registers run-gdbstub-prot-none \
/qemu/target/hexagon/
A DREADME67 RsV, RtV are source registers
184 these functions record the reads and writes to registers by calling ctx_log_*.
209 predicate registers.
247 For example, this packet performs a swap of registers r0 and r1
262 reg_log list of registers written
277 VRegs Vector registers
279 tmp_VRegs Temporary registers *not* stored during commit
280 QRegs Q (vector predicate) registers
/qemu/target/s390x/
A Dcpu_features_def.h.inc152 DEF_FEAT(PLO_CL, "plo-cl", PLO, 0, "PLO Compare and load (32 bit in general registers)")
154 DEF_FEAT(PLO_CLGR, "plo-clgr", PLO, 2, "PLO Compare and load (32 bit in general registers)")
156 DEF_FEAT(PLO_CS, "plo-cs", PLO, 4, "PLO Compare and swap (32 bit in general registers)")
158 DEF_FEAT(PLO_CSGR, "plo-csgr", PLO, 6, "PLO Compare and swap (32 bit in general registers)")
160 DEF_FEAT(PLO_DCS, "plo-dcs", PLO, 8, "PLO Double compare and swap (32 bit in general registers)")
162 DEF_FEAT(PLO_DCSGR, "plo-dcsgr", PLO, 10, "PLO Double compare and swap (32 bit in general registers…
164 …FEAT(PLO_CSST, "plo-csst", PLO, 12, "PLO Compare and swap and store (32 bit in general registers)")
166 …(PLO_CSSTGR, "plo-csstgr", PLO, 14, "PLO Compare and swap and store (32 bit in general registers)")
168 …CSDST, "plo-csdst", PLO, 16, "PLO Compare and swap and double store (32 bit in general registers)")
170 …TGR, "plo-csdstgr", PLO, 18, "PLO Compare and swap and double store (32 bit in general registers)")
[all …]
/qemu/include/hw/dma/
A Dxlnx_dpdma.h40 uint32_t registers[XLNX_DPDMA_REG_ARRAY_SIZE]; member
/qemu/docs/tools/
A Dqemu-vmsr-helper.rst20 However those registers are accessible under privileged access (CAP_SYS_RAWIO).
21 QEMU can use an external helper to access those privileged registers.
/qemu/docs/system/arm/
A Demcraft-sf2.rst12 - System registers
/qemu/target/riscv/insn_trans/
A Dtrans_rvzacas.c.inc68 * Encodings with odd numbered registers specified in rs2 and rd are
106 * Encodings with odd numbered registers specified in rs2 and rd are
/qemu/docs/system/
A Dmonitor.rst30 You can use register names to get the value of specifics CPU registers
/qemu/target/tricore/
A Dcsfr.h.inc94 /* memory management registers */
110 /* debug registers */
/qemu/target/hexagon/imported/
A Dalu.idef28 "Add 32-bit registers",
32 "Subtract 32-bit registers",
44 COND_ALU(A2_pxor,"Rd32=xor(Rs32,Rt32)","Conditionally XOR registers",RdV=RsV^RtV)
45 COND_ALU(A2_pand,"Rd32=and(Rs32,Rt32)","Conditionally AND registers",RdV=RsV&RtV)
46 COND_ALU(A2_por,"Rd32=or(Rs32,Rt32)","Conditionally OR registers",RdV=RsV|RtV)
57 "Add 32-bit registers with saturation",
61 "Subtract 32-bit registers with saturation",
203 "Maximum of two registers",
207 "Maximum of two registers (unsigned)",
211 "Minimum of two registers",
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