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Searched refs:rx_fifo (Results 1 – 25 of 45) sorted by relevance

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/qemu/hw/char/
A Dgoldfish_tty.c53 value = fifo8_num_used(&s->rx_fifo); in goldfish_tty_read()
80 if (!fifo8_is_empty(&s->rx_fifo)) { in goldfish_tty_cmd()
88 if (!fifo8_is_empty(&s->rx_fifo)) { in goldfish_tty_cmd()
111 while (len && !fifo8_is_empty(&s->rx_fifo)) { in goldfish_tty_cmd()
171 int available = fifo8_num_free(&s->rx_fifo); in goldfish_tty_can_receive()
184 g_assert(size <= fifo8_num_free(&s->rx_fifo)); in goldfish_tty_receive()
186 fifo8_push_all(&s->rx_fifo, buffer, size); in goldfish_tty_receive()
199 fifo8_reset(&s->rx_fifo); in goldfish_tty_reset()
211 fifo8_create(&s->rx_fifo, GOLFISH_TTY_BUFFER_SIZE); in goldfish_tty_realize()
228 fifo8_destroy(&s->rx_fifo); in goldfish_tty_unrealize()
[all …]
A Dimx_serial.c48 VMSTATE_FIFO32(rx_fifo, IMXSerialState),
100 if (fifo32_is_full(&s->rx_fifo)) { in imx_serial_rx_fifo_push()
104 if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) { in imx_serial_rx_fifo_push()
108 fifo32_push(&s->rx_fifo, pushed_value); in imx_serial_rx_fifo_push()
114 if (fifo32_is_empty(&s->rx_fifo)) { in imx_serial_rx_fifo_pop()
117 return fifo32_pop(&s->rx_fifo); in imx_serial_rx_fifo_pop()
163 fifo32_reset(&s->rx_fifo); in imx_serial_reset()
198 rx_used = fifo32_num_used(&s->rx_fifo); in imx_serial_read()
370 return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; in imx_can_receive()
380 if (fifo32_num_used(&s->rx_fifo) >= rxtl) { in imx_put_data()
[all …]
A Dsifive_uart.c143 r = s->rx_fifo[0]; in sifive_uart_read()
144 memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); in sifive_uart_read()
223 if (s->rx_fifo_len >= sizeof(s->rx_fifo)) { in sifive_uart_rx()
227 s->rx_fifo[s->rx_fifo_len++] = *buf; in sifive_uart_rx()
236 return s->rx_fifo_len < sizeof(s->rx_fifo); in sifive_uart_can_rx()
296 memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); in sifive_uart_reset_enter()
311 VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
A Dxilinx_uartlite.c64 uint8_t rx_fifo[8]; member
89 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; in uart_update_status()
108 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; in uart_read()
193 s->rx_fifo[s->rx_fifo_pos] = *buf; in uart_rx()
206 return s->rx_fifo_len < sizeof(s->rx_fifo); in uart_can_rx()
A Dsh_serial.c61 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ member
87 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); in OBJECT_DEFINE_TYPE()
268 ret = s->rx_fifo[s->rx_tail++]; in sh_serial_read()
301 ret = s->rx_fifo[0]; in sh_serial_read()
357 s->rx_fifo[s->rx_head++] = buf[i]; in sh_serial_receive1()
375 s->rx_fifo[0] = buf[0]; in sh_serial_receive1()
A Dnrf51_uart.c52 r = s->rx_fifo[s->rx_fifo_pos]; in uart_read()
234 s->rx_fifo[pos] = buf[i]; in uart_receive()
296 VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
/qemu/hw/ssi/
A Dbcm2835_spi.c50 if (!fifo8_is_empty(&s->rx_fifo)) { in bcm2835_spi_update_rx_flags()
57 if (fifo8_is_full(&s->rx_fifo)) { in bcm2835_spi_update_rx_flags()
64 if (fifo8_num_used(&s->rx_fifo) >= FIFO_SIZE_3_4) { in bcm2835_spi_update_rx_flags()
92 while (!fifo8_is_empty(&s->tx_fifo) && !fifo8_is_full(&s->rx_fifo)) { in bcm2835_spi_flush_tx_fifo()
95 fifo8_push(&s->rx_fifo, rx_byte); in bcm2835_spi_flush_tx_fifo()
114 readval = fifo8_pop(&s->rx_fifo); in bcm2835_spi_read()
155 fifo8_reset(&s->rx_fifo); in bcm2835_spi_write()
234 fifo8_create(&s->rx_fifo, FIFO_SIZE); in bcm2835_spi_realize()
241 fifo8_reset(&s->rx_fifo); in bcm2835_spi_reset()
257 VMSTATE_FIFO8(rx_fifo, BCM2835SPIState),
A Dpl022.c108 s->rx_fifo[o] = val & s->bitmask; in pl022_xfer()
134 val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7]; in pl022_read()
241 s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) { in pl022_post_load()
265 VMSTATE_UINT16(rx_fifo[0], PL022State),
267 VMSTATE_UINT16(rx_fifo[1], PL022State),
269 VMSTATE_UINT16(rx_fifo[2], PL022State),
271 VMSTATE_UINT16(rx_fifo[3], PL022State),
273 VMSTATE_UINT16(rx_fifo[4], PL022State),
275 VMSTATE_UINT16(rx_fifo[5], PL022State),
277 VMSTATE_UINT16(rx_fifo[6], PL022State),
[all …]
A Dallwinner-a10-spi.c183 fifo8_reset(&s->rx_fifo); in allwinner_a10_spi_rxfifo_reset()
218 if (fifo8_is_empty(&s->rx_fifo)) { in allwinner_a10_spi_update_irq()
224 if (fifo8_num_used(&s->rx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 2)) { in allwinner_a10_spi_update_irq()
242 if (fifo8_is_full(&s->rx_fifo)) { in allwinner_a10_spi_update_irq()
272 if (fifo8_is_full(&s->rx_fifo)) { in allwinner_a10_spi_update_irq()
317 if (fifo8_is_full(&s->rx_fifo)) { in allwinner_a10_spi_flush_txfifo()
320 fifo8_push(&s->rx_fifo, rx); in allwinner_a10_spi_flush_txfifo()
363 if (fifo8_is_empty(&s->rx_fifo)) { in allwinner_a10_spi_read()
368 value = fifo8_pop(&s->rx_fifo); in allwinner_a10_spi_read()
514 VMSTATE_FIFO8(rx_fifo, AWA10SPIState),
[all …]
A Dxilinx_spi.c96 Fifo8 rx_fifo; member
112 fifo8_reset(&s->rx_fifo); in rxfifo_reset()
133 (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0); in xlx_spi_update_irq()
184 if (fifo8_is_full(&s->rx_fifo)) { in spi_flush_txfifo()
187 fifo8_push(&s->rx_fifo, (uint8_t)rx); in spi_flush_txfifo()
188 if (fifo8_is_full(&s->rx_fifo)) { in spi_flush_txfifo()
213 if (fifo8_is_empty(&s->rx_fifo)) { in spi_read()
219 r = fifo8_pop(&s->rx_fifo); in spi_read()
220 if (fifo8_is_empty(&s->rx_fifo)) { in spi_read()
349 fifo8_create(&s->rx_fifo, FIFO_CAPACITY); in xilinx_spi_realize()
[all …]
A Dimx_spi.c67 VMSTATE_FIFO32(rx_fifo, IMXSPIState),
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
99 if (fifo32_is_full(&s->rx_fifo)) { in imx_spi_update_irq()
168 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
210 if (fifo32_is_full(&s->rx_fifo)) { in imx_spi_flush_txfifo()
213 fifo32_push(&s->rx_fifo, rx); in imx_spi_flush_txfifo()
232 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
297 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_read()
302 value = fifo32_pop(&s->rx_fifo); in imx_spi_read()
[all …]
A Dmss-spi.c97 fifo32_reset(&s->rx_fifo); in rxfifo_reset()
170 if (fifo32_is_empty(&s->rx_fifo)) { in spi_read()
175 ret = fifo32_pop(&s->rx_fifo); in spi_read()
177 if (fifo32_is_empty(&s->rx_fifo)) { in spi_read()
240 if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { in spi_flush_txfifo()
244 fifo32_push(&s->rx_fifo, rx); in spi_flush_txfifo()
246 if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) { in spi_flush_txfifo()
248 } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { in spi_flush_txfifo()
386 fifo32_create(&s->rx_fifo, FIFO_CAPACITY); in mss_spi_realize()
395 VMSTATE_FIFO32(rx_fifo, MSSSpiState),
A Dsifive_spi.c72 fifo8_reset(&s->rx_fifo); in sifive_spi_rxfifo_reset()
99 if (fifo8_num_used(&s->rx_fifo) > s->regs[R_RXMARK]) { in sifive_spi_update_irq()
139 if (!fifo8_is_full(&s->rx_fifo)) { in sifive_spi_flush_txfifo()
141 fifo8_push(&s->rx_fifo, rx); in sifive_spi_flush_txfifo()
201 if (fifo8_is_empty(&s->rx_fifo)) { in sifive_spi_read()
204 r = fifo8_pop(&s->rx_fifo); in sifive_spi_read()
328 fifo8_create(&s->rx_fifo, FIFO_CAPACITY); in sifive_spi_realize()
A Dibex_spi_host.c114 fifo8_reset(&s->rx_fifo); in ibex_spi_rxfifo_reset()
250 } else if (fifo8_is_full(&s->rx_fifo)) { in ibex_spi_host_transfer()
262 if (!fifo8_is_full(&s->rx_fifo)) { in ibex_spi_host_transfer()
263 fifo8_push(&s->rx_fifo, rx); in ibex_spi_host_transfer()
321 if (fifo8_is_empty(&s->rx_fifo)) { in ibex_spi_host_read()
328 rx_byte = fifo8_pop(&s->rx_fifo); in ibex_spi_host_read()
577 VMSTATE_FIFO8(rx_fifo, IbexSPIHostState),
612 fifo8_create(&s->rx_fifo, IBEX_SPI_HOST_RXFIFO_LEN); in ibex_spi_host_realize()
A Dxilinx_spips.c320 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? in xilinx_spips_update_ixr()
371 fifo8_reset(&s->rx_fifo); in xilinx_spips_reset()
372 fifo8_reset(&s->rx_fifo); in xilinx_spips_reset()
662 } else if (fifo8_is_full(&s->rx_fifo)) { in xilinx_spips_flush_txfifo()
673 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); in xilinx_spips_flush_txfifo()
853 recv_fifo = &s->rx_fifo; in xlnx_zynqmp_qspips_notify()
1069 fifo8_reset(&s->rx_fifo); in xilinx_qspips_write()
1170 fifo8_reset(&s->rx_fifo); in lqspi_load_cache()
1199 fifo8_reset(&s->rx_fifo); in lqspi_load_cache()
1311 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); in xilinx_spips_realize()
[all …]
A Dxlnx-versal-ospi.c637 fifo8_push(&s->rx_fifo, tx_rx); in ospi_flush_txfifo()
746 fifo8_reset(&s->rx_fifo); in ospi_ind_read()
893 fifo8_reset(&s->rx_fifo); in ospi_transmit_wel()
910 fifo8_reset(&s->rx_fifo); in ospi_ind_write()
930 fifo8_reset(&s->rx_fifo); in ospi_ind_write()
1020 fifo8_reset(&s->rx_fifo); in ospi_stig_cmd_exec()
1041 fifo8_reset(&s->rx_fifo); in ospi_stig_cmd_exec()
1148 fifo8_reset(&s->rx_fifo); in ospi_do_dac_read()
1188 fifo8_reset(&s->rx_fifo); in ospi_do_dac_write()
1207 fifo8_reset(&s->rx_fifo); in ospi_do_dac_write()
[all …]
/qemu/hw/net/
A Dsmc91c111.c50 int rx_fifo[NUM_PACKETS]; member
79 VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS),
188 s->rx_fifo[i] = s->rx_fifo[i + 1]; in smc91c111_pop_rx_fifo()
411 smc91c111_release_packet(s, s->rx_fifo[0]); in smc91c111_writeb()
448 n = s->rx_fifo[0]; in smc91c111_writeb()
585 return s->rx_fifo[0]; in smc91c111_readb()
596 n = s->rx_fifo[0]; in smc91c111_readb()
705 s->rx_fifo[s->rx_fifo_len++] = packetnum; in smc91c111_receive()
A Dstellaris_enet.c302 uint8_t *rx_fifo; in stellaris_enet_read() local
309 rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset; in stellaris_enet_read()
311 val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16) in stellaris_enet_read()
312 | (rx_fifo[3] << 24); in stellaris_enet_read()
A Dallwinner_emac.c155 fifo8_reset(&s->rx_fifo); in aw_emac_rx_reset()
189 return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532); in aw_emac_can_receive()
196 Fifo8 *fifo = &s->rx_fifo; in aw_emac_receive()
250 Fifo8 *fifo = &s->rx_fifo; in aw_emac_read()
460 fifo8_create(&s->rx_fifo, RX_FIFO_SIZE); in aw_emac_realize()
506 VMSTATE_FIFO8(rx_fifo, AwEmacState),
/qemu/hw/net/can/
A Dxlnx-zynqmp-can.c263 if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > in can_update_irq()
269 if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) { in can_update_irq()
510 if (fifo32_is_full(&s->rx_fifo)) { in transfer_fifo()
514 fifo32_push(&s->rx_fifo, data[i]); in transfer_fifo()
728 if (fifo32_is_full(&s->rx_fifo)) { in update_rx_fifo()
733 fifo32_push(&s->rx_fifo, frame->can_id); in update_rx_fifo()
784 unsigned used = fifo32_num_used(&s->rx_fifo); in can_rxfifo_post_read_id()
790 s->regs[R_RXFIFO_DLC] = fifo32_pop(&s->rx_fifo); in can_rxfifo_post_read_id()
1024 fifo32_reset(&s->rx_fifo); in xlnx_zynqmp_can_reset_hold()
1121 fifo32_create(&s->rx_fifo, RXFIFO_SIZE); in xlnx_zynqmp_can_realize()
[all …]
/qemu/hw/arm/
A Dstrongarm.c941 uint16_t rx_fifo[12]; /* value + error flags in high bits */ member
960 uint16_t ent = s->rx_fifo[s->rx_start]; in strongarm_uart_update_status()
996 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { in strongarm_uart_update_int_status()
1071 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; in strongarm_uart_rx_push()
1074 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; in strongarm_uart_rx_push()
1163 ret = s->rx_fifo[s->rx_start]; in strongarm_uart_read()
1327 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1374 uint16_t rx_fifo[8]; member
1457 retval = s->rx_fifo[s->rx_start++]; in strongarm_ssp_read()
1523 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; in strongarm_ssp_write()
[all …]
/qemu/include/hw/char/
A Dgoldfish_tty.h33 Fifo8 rx_fifo; member
/qemu/include/hw/ssi/
A Dmss-spi.h49 Fifo32 rx_fifo; member
A Dsifive_spi.h45 Fifo8 rx_fifo; member
A Dallwinner-a10-spi.h53 Fifo8 rx_fifo; member

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