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Searched refs:upper (Results 1 – 25 of 58) sorted by relevance

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/qemu/target/sparc/
A Dmonitor.c101 { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
103 { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
105 { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
107 { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
109 { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
111 { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
113 { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
115 { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
117 { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
119 { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
[all …]
A Dgdbstub.c48 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); in sparc_cpu_gdb_read_register()
78 return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); in sparc_cpu_gdb_read_register()
134 env->fpr[(n - 32) / 2].l.upper = tmp; in sparc_cpu_gdb_write_register()
172 env->fpr[(n - 32) / 2].l.upper = tmp; in sparc_cpu_gdb_write_register()
/qemu/include/qemu/
A Dcpu-float.h17 uint32_t upper; member
23 uint32_t upper; member
33 uint16_t upper; member
42 uint32_t upper; member
47 uint64_t upper; member
54 uint32_t upper; member
59 uint64_t upper; member
/qemu/scripts/tracetool/format/
A Dh.py23 '#ifndef TRACE_%s_GENERATED_TRACERS_H' % group.upper(),
24 '#define TRACE_%s_GENERATED_TRACERS_H' % group.upper(),
45 name=e.original.name.upper(),
47 out('#define TRACE_%s_ENABLED %d' % (e.name.upper(), enabled))
91 out('#endif /* TRACE_%s_GENERATED_TRACERS_H */' % group.upper())
A Dust_events_h.py35 '#if !defined (TRACE_%s_GENERATED_UST_H) || \\' % group.upper(),
37 '#define TRACE_%s_GENERATED_UST_H' % group.upper(),
102 out('#endif /* TRACE_%s_GENERATED_UST_H */' % group.upper(),
A Dc.py43 sstate = "TRACE_%s_ENABLED" % e.name.upper(),
/qemu/scripts/tracetool/backend/
A Ddtrace.py62 uppername=e.name.upper())
66 uppername=event.name.upper(),
72 uppername=event.name.upper())
A Dftrace.py48 event_id="TRACE_" + event.name.upper(),
57 event_id="TRACE_" + event.name.upper())
A Dlog.py38 cond = "trace_event_get_state(%s)" % ("TRACE_" + event.name.upper())
66 event_id="TRACE_" + event.name.upper())
A Dsyslog.py37 cond = "trace_event_get_state(%s)" % ("TRACE_" + event.name.upper())
54 event_id="TRACE_" + event.name.upper())
A Dsimple.py46 event_id="TRACE_" + event.name.upper())
75 event_id = 'TRACE_' + event.name.upper()
/qemu/scripts/qapi/
A Dcommands.py79 upper = name.upper()
90 upper=upper, name=name)
131 upper=upper, name=name)
A Dcommon.py64 return c_name(ret.upper()).lstrip('_')
79 return prefix + '_' + c_name(const_name, False).upper()
191 name=c_fname(name).upper())
199 name=c_fname(name).upper())
/qemu/docs/devel/migration/
A Ddirty-limit.rst4 The dirty limit, short for dirty page rate upper limit, is a new capability
36 page rate value and the corresponding upper limit of the VM:
39 last KVM_EXIT_DIRTY_RING_FULL exception; The dirty page rate upper
47 rate progressively down to the upper limit without oscillation. To
/qemu/tests/qtest/
A De1000e-test.c71 g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, ==, in e1000e_send_verify()
122 g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & in e1000e_receive_verify()
A Dpnv-xive2-common.c113 uint64_t upper = xive_get_field32(0x0fffffff, nvp->w6); in get_cl_pair_addr() local
115 return (upper << 32) | (lower << 8); in get_cl_pair_addr()
/qemu/target/m68k/
A Dcpu.c360 *pexp = temp.l.upper; in cpu_get_fp80()
363 static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) in cpu_set_fp80() argument
367 temp.l.upper = upper; in cpu_set_fp80()
/qemu/hw/net/
A De1000e_core.c77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { in e1000e_process_ts_option()
706 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; in e1000e_process_tx_desc()
780 dp->upper.data = cpu_to_le32(txd_upper); in e1000e_txdesc_writeback()
782 &dp->upper, sizeof(dp->upper)); in e1000e_txdesc_writeback()
1258 desc->wb.upper.length = cpu_to_le16(length); in e1000e_write_ext_rx_descr()
1264 &desc->wb.upper.status_error, in e1000e_write_ext_rx_descr()
1266 &desc->wb.upper.vlan); in e1000e_write_ext_rx_descr()
1295 desc->wb.upper.header_status = in e1000e_write_ps_rx_descr()
1358 wb.upper.status_error); in e1000e_pci_dma_write_rx_desc()
1359 uint32_t status = d->wb.upper.status_error; in e1000e_pci_dma_write_rx_desc()
[all …]
A De1000.c665 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; in process_tx_desc()
680 le16_to_cpu(dp->upper.fields.special)); in process_tx_desc()
737 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & in txdesc_writeback()
739 dp->upper.data = cpu_to_le32(txd_upper); in txdesc_writeback()
740 pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp), in txdesc_writeback()
741 &dp->upper, sizeof(dp->upper)); in txdesc_writeback()
778 desc.upper.data); in start_xmit()
A De1000_regs.h293 } upper; member
/qemu/ui/
A Dvnc-enc-tight.c556 int here[3], upper[3], left[3], upperleft[3]; in tight_filter_gradient24() local
575 upper[c] = 0; in tight_filter_gradient24()
582 upperleft[c] = upper[c]; in tight_filter_gradient24()
584 upper[c] = *prev; in tight_filter_gradient24()
588 prediction = left[c] + upper[c] - upperleft[c]; in tight_filter_gradient24()
614 int here[3], upper[3], left[3], upperleft[3]; \
631 upper[c] = 0; \
642 upperleft[c] = upper[c]; \
644 upper[c] = *prev; \
648 prediction = left[c] + upper[c] - upperleft[c]; \
/qemu/scripts/codeconverter/codeconverter/
A Dtest_patching.py21 return self.group(0)[1].upper()*5
/qemu/tests/qemu-iotests/
A D25741 upper = (self.offset + self.size - 1) // granularity
42 return set(range(lower, upper + 1))
/qemu/docs/system/
A Dtarget-i386-desc.rst.inc39 SMP is supported with a large number of virtual CPUs (upper limit is
/qemu/hw/pci/
A Dpci_bridge.c96 uint32_t base, uint32_t upper) in pci_config_get_pref_base() argument
104 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; in pci_config_get_pref_base()

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