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Searched refs:APB0_SRC_PLL_PERIPH0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Dclock_sun9i.c50 writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8), in clock_init_safe()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun9i.h164 #define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT) macro

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