| /u-boot/board/freescale/mpc8548cds/ |
| A D | tlb.c | 14 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
17 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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| /u-boot/board/socrates/ |
| A D | tlb.c | 17 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
20 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
23 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
26 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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| /u-boot/board/freescale/p1010rdb/ |
| A D | tlb.c | 11 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
14 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
15 CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
19 CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
23 CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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| /u-boot/include/configs/ |
| A D | stmark2.h | 46 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
80 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
82 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
95 #define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | socfpga_common.h | 15 #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 macro
18 #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 macro
30 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
31 (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
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| A D | amcore.h | 33 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
59 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
61 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5272C3.h | 56 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
86 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
88 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5275EVB.h | 66 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
95 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
97 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5208EVBE.h | 46 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
88 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
90 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5235EVB.h | 57 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
98 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
100 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5249EVB.h | 43 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
83 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
85 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5282EVB.h | 59 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
93 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
95 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M53017EVB.h | 60 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
105 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
107 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | cobra5272.h | 113 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
148 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
150 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5329EVB.h | 54 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
105 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
107 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | M5373EVB.h | 56 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
105 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
107 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | eb_cpu5282.h | 57 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
94 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
96 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | zynq_cse.h | 17 #undef CFG_SYS_INIT_RAM_ADDR
19 #define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000 macro
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| A D | aspeed-common.h | 20 #define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) macro
23 #define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) macro
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| A D | M5253DEMO.h | 64 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 macro
102 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
104 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | astro_mcf5373l.h | 117 #define CFG_SYS_INIT_RAM_ADDR 0x80000000 macro
176 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
178 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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| A D | at91sam9260ek.h | 39 # define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM macro
41 # define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 macro
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | tlb.c | 11 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
15 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
19 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
23 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
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| /u-boot/board/keymile/kmcent2/ |
| A D | tlb.c | 14 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
18 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
22 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
26 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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| /u-boot/board/freescale/t102xrdb/ |
| A D | tlb.c | 11 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
15 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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