Searched refs:CK_TOP_CB_MM_D2 (Results 1 – 4 of 4) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7986.c | 55 PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
173 CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
179 CK_TOP_CB_MM_D2 };
189 CK_TOP_CB_MM_D2 };
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| A D | clk-mt7981.c | 57 PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
175 CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
192 static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
211 CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7986-clk.h | 61 #define CK_TOP_CB_MM_D2 7 macro
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| A D | mt7981-clk.h | 63 #define CK_TOP_CB_MM_D2 9 macro
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